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debug开始，cdrin优化后payloadlen加载错误

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This commit is contained in:
RuigeLee
2024-11-01 18:09:16 +08:00
parent 65491c74f6
commit 983f9e771d
4 changed files with 14 additions and 13 deletions
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14
src/main/scala/backBoard/pico/BackSystem.scala
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@@ -159,19 +159,17 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(11) === "b1".U & ~pico.io.mem.instr
pico.io.mem.ready :=
Mux( pico.io.mem.instr, sram.io.mem.ready,
Mux( pico.io.mem.instr | pico.io.mem.addr.extract(31) === "b1".U, sram.io.mem.ready,
Mux1H(Seq(
( pico.io.mem.addr.extract(31) === "b1".U ) -> sram.io.mem.ready,
( pico.io.mem.addr.extract(11) === "b0".U ) -> cdr.io.mem.ready,
( pico.io.mem.addr.extract(11) === "b1".U ) -> gpio.io.mem.ready,
( pico.io.mem.addr.extract(10) === "b0".U ) -> cdr.io.mem.ready,
( pico.io.mem.addr.extract(10) === "b1".U ) -> gpio.io.mem.ready,
))
)
pico.io.mem.rdata :=
Mux( pico.io.mem.instr, sram.io.mem.rdata,
Mux( pico.io.mem.instr | pico.io.mem.addr.extract(31) === "b1".U, sram.io.mem.rdata,
Mux1H(Seq(
( pico.io.mem.addr.extract(31) === "b1".U ) -> sram.io.mem.rdata,
( pico.io.mem.addr.extract(11) === "b0".U ) -> cdr.io.mem.rdata,
( pico.io.mem.addr.extract(11) === "b1".U ) -> gpio.io.mem.rdata,
( pico.io.mem.addr.extract(10) === "b0".U ) -> cdr.io.mem.rdata,
( pico.io.mem.addr.extract(10) === "b1".U ) -> gpio.io.mem.rdata,
))
)

5
src/main/scala/backBoard/pico/TLCDR.scala
View File

@@ -63,7 +63,10 @@ trait TLCDRTx{ this: TLCDRBase =>
when( txFifo.io.deq.fire ){ //txCnt === 3.U
txData := txFifo.io.deq.bits
assert(CDROut.io.axis.fire)
when( isTxBusy ){
assert(CDROut.io.axis.fire)
}
} .elsewhen( CDROut.io.axis.fire ){
txData := txData << 8
}