From 983f9e771d166f49c4883c14a21c78e3c110c8a5 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Fri, 1 Nov 2024 18:09:16 +0800 Subject: [PATCH] =?UTF-8?q?debug=E5=BC=80=E5=A7=8B=EF=BC=8Ccdrin=E4=BC=98?= =?UTF-8?q?=E5=8C=96=E5=90=8Epayloadlen=E5=8A=A0=E8=BD=BD=E9=94=99?= =?UTF-8?q?=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 2 +- src/main/scala/backBoard/pico/BackSystem.scala | 14 ++++++-------- src/main/scala/backBoard/pico/TLCDR.scala | 5 ++++- tb/sw/src/SlvMain.c | 6 +++--- 4 files changed, 14 insertions(+), 13 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 5671b5b..2989623 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -92,7 +92,7 @@ trait CDRInAxis{ this: CDRInBase => val shiftData = checkSFD(7,0) //RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat) - val payloadLen = RegEnable( shiftData, byteCnt === 0.U & bitCnt === 7.U & stateCurr === STATE_HEADER ) + val payloadLen = RegEnable( shiftData, byteCnt === 0.U & bitCnt === 7.U & stateCurr === STATE_HEADER ) val isArbLock: Bool diff --git a/src/main/scala/backBoard/pico/BackSystem.scala b/src/main/scala/backBoard/pico/BackSystem.scala index 710221e..33310c9 100644 --- a/src/main/scala/backBoard/pico/BackSystem.scala +++ b/src/main/scala/backBoard/pico/BackSystem.scala @@ -159,19 +159,17 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(11) === "b1".U & ~pico.io.mem.instr pico.io.mem.ready := - Mux( pico.io.mem.instr, sram.io.mem.ready, + Mux( pico.io.mem.instr | pico.io.mem.addr.extract(31) === "b1".U, sram.io.mem.ready, Mux1H(Seq( - ( pico.io.mem.addr.extract(31) === "b1".U ) -> sram.io.mem.ready, - ( pico.io.mem.addr.extract(11) === "b0".U ) -> cdr.io.mem.ready, - ( pico.io.mem.addr.extract(11) === "b1".U ) -> gpio.io.mem.ready, + ( pico.io.mem.addr.extract(10) === "b0".U ) -> cdr.io.mem.ready, + ( pico.io.mem.addr.extract(10) === "b1".U ) -> gpio.io.mem.ready, )) ) pico.io.mem.rdata := - Mux( pico.io.mem.instr, sram.io.mem.rdata, + Mux( pico.io.mem.instr | pico.io.mem.addr.extract(31) === "b1".U, sram.io.mem.rdata, Mux1H(Seq( - ( pico.io.mem.addr.extract(31) === "b1".U ) -> sram.io.mem.rdata, - ( pico.io.mem.addr.extract(11) === "b0".U ) -> cdr.io.mem.rdata, - ( pico.io.mem.addr.extract(11) === "b1".U ) -> gpio.io.mem.rdata, + ( pico.io.mem.addr.extract(10) === "b0".U ) -> cdr.io.mem.rdata, + ( pico.io.mem.addr.extract(10) === "b1".U ) -> gpio.io.mem.rdata, )) ) diff --git a/src/main/scala/backBoard/pico/TLCDR.scala b/src/main/scala/backBoard/pico/TLCDR.scala index bc69461..16f6760 100644 --- a/src/main/scala/backBoard/pico/TLCDR.scala +++ b/src/main/scala/backBoard/pico/TLCDR.scala @@ -63,7 +63,10 @@ trait TLCDRTx{ this: TLCDRBase => when( txFifo.io.deq.fire ){ //txCnt === 3.U txData := txFifo.io.deq.bits - assert(CDROut.io.axis.fire) + when( isTxBusy ){ + assert(CDROut.io.axis.fire) + } + } .elsewhen( CDROut.io.axis.fire ){ txData := txData << 8 } diff --git a/tb/sw/src/SlvMain.c b/tb/sw/src/SlvMain.c index 188bd56..3e266ad 100644 --- a/tb/sw/src/SlvMain.c +++ b/tb/sw/src/SlvMain.c @@ -14,9 +14,9 @@ volatile uint32_t *cdr_rxLen = (uint32_t*)( 0x000 + 0x18 ); //read volatile uint32_t *cdr_rxFifo = (uint32_t*)( 0x000 + 0x1c ); //read -volatile uint32_t *WriteGpio = (uint32_t*) ( 0x800); -volatile uint32_t *ReadGpio = (uint32_t*) ( 0x800); -volatile uint32_t *ReadIsLast = (uint32_t*) ( 0x808); +volatile uint32_t *WriteGpio = (uint32_t*) ( 0x400); +volatile uint32_t *ReadGpio = (uint32_t*) ( 0x400); +volatile uint32_t *ReadIsLast = (uint32_t*) ( 0x408);