从站下行写完
This commit is contained in:
RuigeLee
@@ -76,9 +76,9 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
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val headByte = Header_Info_Bundle.getWidth()/8
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require( headLen == 8 )
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require( headByte == 8 )
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val testIOShift = ShiftRegisters(io.testIO, headLen/2 + 1, false.B, true.B)
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val testIOShift = ShiftRegisters(io.testIO, headByte/2 + 1, false.B, true.B)
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val sendHeader = Reg( new Header_Info_Bundle )
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@@ -14,11 +14,19 @@ abstract class ShinSlvPhyBase extends Module{
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val downRegTemp = Reg(Vec( 32, UInt(8.W) ))
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val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
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val headByte = Header_Info_Bundle.getWidth()/8
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require( headByte == 8 )
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require( headByte > 4, "At Least 4 more additional cycles to ensure CRC Failure boardcast to next nodes!\n")
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val OpInitByte = 1.U
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val OpBoardCastByte = 16.U
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val OpUniCastByte = 32.U
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val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte
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}
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trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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val headByte = Header_Info_Bundle.getWidth()/8
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require( headLen == 8 )
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val DownRecvStateIdle = 0.U
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val DownRecvStateOHead = 1.U
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@@ -26,35 +34,39 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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val DownRecvStateFData = 3.U
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val DownRecvStateCRC = 4.U
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val DownRecvStateIdle = 0.U
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val DownRecvStateNHead = 1.U
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val DownRecvStateFData = 2.U
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val DownSendStateIdle = 0.U
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val DownSendStateNHead = 1.U
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val DownSendStateFData = 2.U
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val downOldHead = Reg( new Header_Info_Bundle )
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val downNewHead = Reg( new Header_Info_Bundle )
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val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 ) )
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val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + 4 ) )
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val downRecvSteteNext = Wire( UInt(3.W) )
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val downRecvStateCurr = RegNext( downRecvSteteNext, 0.U )
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val downRecvCnt = Reg(UInt(10.W))
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val downSendCnt = Reg(UInt(10.W))
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val selfDataByte = Mux1H(Seq(
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downOldHead. ===
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(downOldHead.operator === 0.U) -> OpInitByte,
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(downOldHead.operator === 1.U) -> OpBoardCastByte,
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(downOldHead.operator === 2.U) -> OpUniCastByte,
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))
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val isDownStreamError = RegInit( false.B )
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val forwardDataByte = downNewHead.length
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downRecvSteteNext := Mux1H(Seq(
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(downRecvStateCurr === DownRecvStateIdle ) -> Mux( downStreamCdrIn.io.axis.valid, DownRecvStateOHead, DownRecvStateIdle ),
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(downRecvStateCurr === DownRecvStateOHead) -> Mux( downRecvCnt === ((headByte)-1).U & downStreamCdrIn.io.axis.fire, DownRecvStateSData, DownRecvStateOHead ),
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(downRecvStateCurr === DownRecvStateSData) -> Mux( downRecvCnt === (selfDataByte -1.U) & downStreamCdrIn.io.axis.fire, DownRecvStateFData, DownRecvStateSData),
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(downRecvStateCurr === DownRecvStateFData) -> Mux( downRecvCnt === (forwardDataByte -1.U) & downStreamCdrIn.io.axis.fire, DownRecvStateCRC, DownRecvStateFData),
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(downRecvStateCurr === DownRecvStateCRC ) -> Mux( ~downStreamCdrIn.io.axis.valid, DownRecvStateIdle, DownRecvStateCRC ),
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(downRecvStateCurr === DownRecvStateOHead) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === ((headByte)-1).U, DownRecvStateSData, DownRecvStateOHead), DownRecvStateIdle ), DownRecvStateOHead),
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(downRecvStateCurr === DownRecvStateSData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (selfDataByte -1.U), DownRecvStateFData, DownRecvStateSData), DownRecvStateIdle ), DownRecvStateSData),
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(downRecvStateCurr === DownRecvStateFData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (forwardDataByte -1.U) , DownRecvStateCRC, DownRecvStateFData), DownRecvStateIdle ), DownRecvStateFData),
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(downRecvStateCurr === DownRecvStateCRC ) -> Mux( downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast, DownRecvStateIdle, DownRecvStateCRC ),
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))
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when( downRecvStateCurr =/= downRecvSteteNext ){
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@@ -71,8 +83,8 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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//---------------
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when( downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData ){
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val isNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍
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when( isNewHeadCreated ){
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downNewHead.length := Mux( downOldHead.length >= selfDataByte, downOldHead.length - selfDataByte, 0.U )
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downNewHead.operator := downOldHead.operator
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downNewHead.param := downOldHead.param
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@@ -84,10 +96,11 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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}
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//---------------
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downStreamFifo.io.enq.valid :=
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downRecvStateCurr === DownRecvStateFData & downStreamCdrIn.io.axis.valid
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downStreamFifo.io.enq.bits := downStreamCdrIn.io.axis.bits
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downStreamFifo.io.enq.bits.tdata := downStreamCdrIn.io.axis.bits.tdata
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downStreamFifo.io.enq.bits.tuser := downStreamCdrIn.io.axis.bits.tuser
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downStreamFifo.io.enq.bits.tlast := downRecvCnt === (forwardDataByte -1.U) | downStreamCdrIn.io.axis.bits.tlast
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downStreamCdrIn.io.axis.ready :=
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(downRecvStateCurr === DownRecvStateOHead) |
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@@ -95,42 +108,212 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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(downRecvStateCurr === DownRecvStateFData) |
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(downRecvStateCurr === DownRecvStateCRC )
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when( downRecvStateCurr === DownRecvStateIdle & downRecvSteteNext === DownRecvStateOHead){
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isDownStreamError := false.B
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} .elsewhen( downStreamFifo.io.enq.fire & downStreamFifo.io.enq.bits.tuser ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateOHead ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateSHead & downRecvSteteNext === DownRecvStateOHead ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateFHead & downRecvSteteNext === DownRecvStateOHead ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received, That could not happened!\n")
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}
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assert( ~(downRecvStateCurr === DownRecvStateFData & ~downStreamFifo.io.enq.ready), "Assert Failed, downStream Forward Fifo is OverFlow!" )
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val downSendSteteNext = Wire( UInt(3.W) )
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val downSendStateCurr = RegNext( downSendSteteNext, 0.U )
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downSendSteteNext := Mux1H(Seq(
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( downSendStateCurr === DownSendStateIdle ) -> Mux( isNewHeadCreated, DownSendStateNHead, DownSendStateIdle ),
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( downSendStateCurr === DownSendStateNHead ) -> Mux( downSendCnt === ((headByte)-1).U & downStreamCdrOut.io.axis.fire, DownSendStateFData, DownSendStateNHead ),
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( downSendStateCurr === DownSendStateFData ) -> Mux( downSendCnt === (forwardDataByte -1.U) & downStreamCdrOut.io.axis.fire, DownSendStateIdle, DownSendStateFData),
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))
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when( downSendStateCurr =/= downSendSteteNext ){
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downSendCnt := 0.U
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} .elsewhen( downStreamCdrOut.io.axis.fire ){
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downSendCnt := downSendCnt + 1.U
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}
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downStreamCdrOut.io.axis.valid :=
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downSendStateCurr === DownSendStateNHead | downSendStateCurr === DownSendStateFData
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downStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
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( downSendStateCurr === DownSendStateNHead ) -> (downNewHead.asUInt << (downSendCnt << 3)).head(8),
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( downSendStateCurr === DownSendStateFData ) -> downStreamFifo.io.deq.bits.tdata,
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))
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downStreamCdrOut.io.axis.bits.tlast := ( downSendStateCurr === DownSendStateFData ) & downStreamFifo.io.deq.bits.tlast
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downStreamCdrOut.io.axis.bits.tuser :=
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(( downSendStateCurr === DownSendStateFData ) & downStreamFifo.io.deq.bits.tuser ) |
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isDownStreamError
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downStreamFifo.io.deq.ready :=
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downSendStateCurr === DownSendStateFData & downStreamCdrOut.io.axis.ready
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//got old header
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//create new header
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//got self data
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//forward downStream Data
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downStreamCdrIn.io.axis <> downStreamFifo.io.enq
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downStreamFifo.io.deq <> downStreamCdrOut.io.axis
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assert( ~(downStreamCdrIn.io.axis.valid & ~downStreamCdrIn.io.axis.ready) )
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}
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trait ShinSlvPhyUpStream{ this: ShinSlvPhyBase =>
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val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 ) )
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upStreamCdrIn.io.axis <> upStreamFifo.io.enq
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upStreamFifo.io.deq <> upStreamCdrOut.io.axis
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assert( ~(upStreamCdrIn.io.axis.valid & ~upStreamCdrIn.io.axis.ready) )
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val UpRecvStateIdle = 0.U
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val UpRecvStateOHead = 1.U
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val UpRecvStateFData = 2.U
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val UpRecvStateCRC = 3.U
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val UpSendStateIdle = 0.U
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val UpSendStateNHead = 1.U
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val UpSendStateSHead = 2.U
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val UpSendStateFData = 3.U
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val upOldHead = Reg( new Header_Info_Bundle )
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val upNewHead = Reg( new Header_Info_Bundle )
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val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) ) //4 is reserve
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val upRecvSteteNext = Wire( UInt(3.W) )
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val upRecvStateCurr = RegNext( upRecvSteteNext, 0.U )
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val upRecvCnt = Reg(UInt(10.W))
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val upSendCnt = Reg(UInt(10.W))
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upRecvSteteNext := Mux1H(Seq(
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(upRecvStateCurr === UpRecvStateIdle ) -> Mux( upStreamCdrIn.io.axis.valid, UpRecvStateOHead, UpRecvStateIdle ),
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(upRecvStateCurr === UpRecvStateOHead) -> Mux( upStreamCdrIn.io.axis.fire, Mux( ~upStreamCdrIn.io.axis.bits.tlast, Mux( upRecvCnt === ((headByte)-1).U, UpRecvStateFData, UpRecvStateOHead), UpRecvStateIdle), UpRecvStateOHead ),
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(upRecvStateCurr === UpRecvStateFData) -> Mux( upStreamCdrIn.io.axis.fire, Mux( ~upStreamCdrIn.io.axis.bits.tlast, Mux( upRecvCnt === (upOldHead.length - 1.U), UpRecvStateCRC, UpRecvStateFData), UpRecvStateIdle), UpRecvStateFData ),
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(upRecvStateCurr === UpRecvStateCRC ) -> Mux( upStreamCdrIn.io.axis.fire & upStreamCdrIn.io.axis.bits.tlast, UpRecvStateIdle, UpRecvStateCRC ),
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))
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when( upRecvStateCurr =/= upRecvSteteNext){
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upRecvCnt := 0.U
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} .elsewhen( upStreamCdrIn.io.axis.fire ){
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upRecvCnt := upRecvCnt + 1.U
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}
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// val selfDataByte = Mux1H(Seq(
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// (downOldHead.operator === 0.U) -> OpInitByte,
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// (downOldHead.operator === 1.U) -> OpBoardCastByte,
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// (downOldHead.operator === 2.U) -> OpUniCastByte,
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// ))
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// val isDownStreamError = RegInit( false.B )
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// val forwardDataByte = downNewHead.length
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// when( downRecvStateCurr =/= downRecvSteteNext ){
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// downRecvCnt := 0.U
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// } .elsewhen( downStreamCdrIn.io.axis.fire ){
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// downRecvCnt := downRecvCnt + 1.U
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// }
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// //---------------
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// when( downRecvStateCurr === DownRecvStateOHead & downStreamCdrIn.io.axis.fire ){
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// downOldHead := Cat( downOldHead.asUInt.tail(8), downStreamCdrIn.io.axis.tdata ).asTypeOf(Header_Info_Bundle)
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// }
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// //---------------
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// val isNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍
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// when( isNewHeadCreated ){
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// downNewHead.length := Mux( downOldHead.length >= selfDataByte, downOldHead.length - selfDataByte, 0.U )
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// downNewHead.operator := downOldHead.operator
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// downNewHead.param := downOldHead.param
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// }
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// when( downRecvStateCurr === DownRecvStateSData & downStreamCdrIn.io.axis.fire ){
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// downRegTemp(downRecvCnt) := downStreamCdrIn.io.axis.tdata
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// }
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// //---------------
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// downStreamFifo.io.enq.valid :=
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// downRecvStateCurr === DownRecvStateFData & downStreamCdrIn.io.axis.valid
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// downStreamFifo.io.enq.bits.tdata := downStreamCdrIn.io.axis.bits.tdata
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// downStreamFifo.io.enq.bits.tuser := downStreamCdrIn.io.axis.bits.tuser
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// downStreamFifo.io.enq.bits.tlast := downRecvCnt === (forwardDataByte -1.U) | downStreamCdrIn.io.axis.bits.tlast
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// downStreamCdrIn.io.axis.ready :=
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// (downRecvStateCurr === DownRecvStateOHead) |
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// (downRecvStateCurr === DownRecvStateSData) |
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// (downRecvStateCurr === DownRecvStateFData) |
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// (downRecvStateCurr === DownRecvStateCRC )
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// when( downRecvStateCurr === DownRecvStateIdle & downRecvSteteNext === DownRecvStateOHead){
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// isDownStreamError := false.B
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// } .elsewhen( downStreamFifo.io.enq.fire & downStreamFifo.io.enq.bits.tuser ){
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// isDownStreamError := true.B
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// printf("Warning, Wrong Package Received, That could not happened!\n")
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// } .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateOHead ){
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// isDownStreamError := true.B
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// printf("Warning, Wrong Package Received, That could not happened!\n")
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// } .elsewhen( downRecvStateCurr === DownRecvStateSHead & downRecvSteteNext === DownRecvStateOHead ){
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// isDownStreamError := true.B
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// printf("Warning, Wrong Package Received, That could not happened!\n")
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// } .elsewhen( downRecvStateCurr === DownRecvStateFHead & downRecvSteteNext === DownRecvStateOHead ){
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// isDownStreamError := true.B
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// printf("Warning, Wrong Package Received, That could not happened!\n")
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// } .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){
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// isDownStreamError := true.B
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// printf("Warning, Wrong Package Received, That could not happened!\n")
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// }
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// assert( ~(downRecvStateCurr === DownRecvStateFData & ~downStreamFifo.io.enq.ready), "Assert Failed, downStream Forward Fifo is OverFlow!" )
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}
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