diff --git a/src/main/scala/backBoard/shin/ShinMst.scala b/src/main/scala/backBoard/shin/ShinMst.scala index a86d678..383c574 100644 --- a/src/main/scala/backBoard/shin/ShinMst.scala +++ b/src/main/scala/backBoard/shin/ShinMst.scala @@ -76,9 +76,9 @@ trait ShinMstSend{ this: ShinMstPhyBase => val headByte = Header_Info_Bundle.getWidth()/8 - require( headLen == 8 ) + require( headByte == 8 ) - val testIOShift = ShiftRegisters(io.testIO, headLen/2 + 1, false.B, true.B) + val testIOShift = ShiftRegisters(io.testIO, headByte/2 + 1, false.B, true.B) val sendHeader = Reg( new Header_Info_Bundle ) diff --git a/src/main/scala/backBoard/shin/ShinSlv.scala b/src/main/scala/backBoard/shin/ShinSlv.scala index 78bef50..431f606 100644 --- a/src/main/scala/backBoard/shin/ShinSlv.scala +++ b/src/main/scala/backBoard/shin/ShinSlv.scala @@ -14,11 +14,19 @@ abstract class ShinSlvPhyBase extends Module{ val downRegTemp = Reg(Vec( 32, UInt(8.W) )) val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)})) + val headByte = Header_Info_Bundle.getWidth()/8 + require( headByte == 8 ) + require( headByte > 4, "At Least 4 more additional cycles to ensure CRC Failure boardcast to next nodes!\n") + + val OpInitByte = 1.U + val OpBoardCastByte = 16.U + val OpUniCastByte = 32.U + + val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte + } trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => - val headByte = Header_Info_Bundle.getWidth()/8 - require( headLen == 8 ) val DownRecvStateIdle = 0.U val DownRecvStateOHead = 1.U @@ -26,35 +34,39 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => val DownRecvStateFData = 3.U val DownRecvStateCRC = 4.U - val DownRecvStateIdle = 0.U - val DownRecvStateNHead = 1.U - val DownRecvStateFData = 2.U + + val DownSendStateIdle = 0.U + val DownSendStateNHead = 1.U + val DownSendStateFData = 2.U val downOldHead = Reg( new Header_Info_Bundle ) val downNewHead = Reg( new Header_Info_Bundle ) - val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 ) ) + val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + 4 ) ) val downRecvSteteNext = Wire( UInt(3.W) ) val downRecvStateCurr = RegNext( downRecvSteteNext, 0.U ) val downRecvCnt = Reg(UInt(10.W)) + val downSendCnt = Reg(UInt(10.W)) val selfDataByte = Mux1H(Seq( - downOldHead. === + (downOldHead.operator === 0.U) -> OpInitByte, + (downOldHead.operator === 1.U) -> OpBoardCastByte, + (downOldHead.operator === 2.U) -> OpUniCastByte, )) - + val isDownStreamError = RegInit( false.B ) val forwardDataByte = downNewHead.length downRecvSteteNext := Mux1H(Seq( (downRecvStateCurr === DownRecvStateIdle ) -> Mux( downStreamCdrIn.io.axis.valid, DownRecvStateOHead, DownRecvStateIdle ), - (downRecvStateCurr === DownRecvStateOHead) -> Mux( downRecvCnt === ((headByte)-1).U & downStreamCdrIn.io.axis.fire, DownRecvStateSData, DownRecvStateOHead ), - (downRecvStateCurr === DownRecvStateSData) -> Mux( downRecvCnt === (selfDataByte -1.U) & downStreamCdrIn.io.axis.fire, DownRecvStateFData, DownRecvStateSData), - (downRecvStateCurr === DownRecvStateFData) -> Mux( downRecvCnt === (forwardDataByte -1.U) & downStreamCdrIn.io.axis.fire, DownRecvStateCRC, DownRecvStateFData), - (downRecvStateCurr === DownRecvStateCRC ) -> Mux( ~downStreamCdrIn.io.axis.valid, DownRecvStateIdle, DownRecvStateCRC ), + (downRecvStateCurr === DownRecvStateOHead) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === ((headByte)-1).U, DownRecvStateSData, DownRecvStateOHead), DownRecvStateIdle ), DownRecvStateOHead), + (downRecvStateCurr === DownRecvStateSData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (selfDataByte -1.U), DownRecvStateFData, DownRecvStateSData), DownRecvStateIdle ), DownRecvStateSData), + (downRecvStateCurr === DownRecvStateFData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (forwardDataByte -1.U) , DownRecvStateCRC, DownRecvStateFData), DownRecvStateIdle ), DownRecvStateFData), + (downRecvStateCurr === DownRecvStateCRC ) -> Mux( downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast, DownRecvStateIdle, DownRecvStateCRC ), )) when( downRecvStateCurr =/= downRecvSteteNext ){ @@ -63,16 +75,16 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => downRecvCnt := downRecvCnt + 1.U } -//--------------- + //--------------- when( downRecvStateCurr === DownRecvStateOHead & downStreamCdrIn.io.axis.fire ){ downOldHead := Cat( downOldHead.asUInt.tail(8), downStreamCdrIn.io.axis.tdata ).asTypeOf(Header_Info_Bundle) } -//--------------- - - when( downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData ){ + //--------------- + val isNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍 + when( isNewHeadCreated ){ downNewHead.length := Mux( downOldHead.length >= selfDataByte, downOldHead.length - selfDataByte, 0.U ) downNewHead.operator := downOldHead.operator downNewHead.param := downOldHead.param @@ -83,11 +95,12 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => downRegTemp(downRecvCnt) := downStreamCdrIn.io.axis.tdata } -//--------------- - + //--------------- downStreamFifo.io.enq.valid := downRecvStateCurr === DownRecvStateFData & downStreamCdrIn.io.axis.valid - downStreamFifo.io.enq.bits := downStreamCdrIn.io.axis.bits + downStreamFifo.io.enq.bits.tdata := downStreamCdrIn.io.axis.bits.tdata + downStreamFifo.io.enq.bits.tuser := downStreamCdrIn.io.axis.bits.tuser + downStreamFifo.io.enq.bits.tlast := downRecvCnt === (forwardDataByte -1.U) | downStreamCdrIn.io.axis.bits.tlast downStreamCdrIn.io.axis.ready := (downRecvStateCurr === DownRecvStateOHead) | @@ -95,42 +108,212 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => (downRecvStateCurr === DownRecvStateFData) | (downRecvStateCurr === DownRecvStateCRC ) + when( downRecvStateCurr === DownRecvStateIdle & downRecvSteteNext === DownRecvStateOHead){ + isDownStreamError := false.B + } .elsewhen( downStreamFifo.io.enq.fire & downStreamFifo.io.enq.bits.tuser ){ + isDownStreamError := true.B + printf("Warning, Wrong Package Received, That could not happened!\n") + } .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateOHead ){ + isDownStreamError := true.B + printf("Warning, Wrong Package Received, That could not happened!\n") + } .elsewhen( downRecvStateCurr === DownRecvStateSHead & downRecvSteteNext === DownRecvStateOHead ){ + isDownStreamError := true.B + printf("Warning, Wrong Package Received, That could not happened!\n") + } .elsewhen( downRecvStateCurr === DownRecvStateFHead & downRecvSteteNext === DownRecvStateOHead ){ + isDownStreamError := true.B + printf("Warning, Wrong Package Received, That could not happened!\n") + } .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){ + isDownStreamError := true.B + printf("Warning, Wrong Package Received, That could not happened!\n") + } + + + assert( ~(downRecvStateCurr === DownRecvStateFData & ~downStreamFifo.io.enq.ready), "Assert Failed, downStream Forward Fifo is OverFlow!" ) + + val downSendSteteNext = Wire( UInt(3.W) ) val downSendStateCurr = RegNext( downSendSteteNext, 0.U ) + downSendSteteNext := Mux1H(Seq( + ( downSendStateCurr === DownSendStateIdle ) -> Mux( isNewHeadCreated, DownSendStateNHead, DownSendStateIdle ), + ( downSendStateCurr === DownSendStateNHead ) -> Mux( downSendCnt === ((headByte)-1).U & downStreamCdrOut.io.axis.fire, DownSendStateFData, DownSendStateNHead ), + ( downSendStateCurr === DownSendStateFData ) -> Mux( downSendCnt === (forwardDataByte -1.U) & downStreamCdrOut.io.axis.fire, DownSendStateIdle, DownSendStateFData), + )) + + when( downSendStateCurr =/= downSendSteteNext ){ + downSendCnt := 0.U + } .elsewhen( downStreamCdrOut.io.axis.fire ){ + downSendCnt := downSendCnt + 1.U + } + + downStreamCdrOut.io.axis.valid := + downSendStateCurr === DownSendStateNHead | downSendStateCurr === DownSendStateFData + + downStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq( + ( downSendStateCurr === DownSendStateNHead ) -> (downNewHead.asUInt << (downSendCnt << 3)).head(8), + ( downSendStateCurr === DownSendStateFData ) -> downStreamFifo.io.deq.bits.tdata, + )) + + downStreamCdrOut.io.axis.bits.tlast := ( downSendStateCurr === DownSendStateFData ) & downStreamFifo.io.deq.bits.tlast + downStreamCdrOut.io.axis.bits.tuser := + (( downSendStateCurr === DownSendStateFData ) & downStreamFifo.io.deq.bits.tuser ) | + isDownStreamError + downStreamFifo.io.deq.ready := + downSendStateCurr === DownSendStateFData & downStreamCdrOut.io.axis.ready - - //got old header - - - - //create new header - - - //got self data - - //forward downStream Data - - - - downStreamCdrIn.io.axis <> downStreamFifo.io.enq - downStreamFifo.io.deq <> downStreamCdrOut.io.axis assert( ~(downStreamCdrIn.io.axis.valid & ~downStreamCdrIn.io.axis.ready) ) } trait ShinSlvPhyUpStream{ this: ShinSlvPhyBase => - val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 ) ) - upStreamCdrIn.io.axis <> upStreamFifo.io.enq - upStreamFifo.io.deq <> upStreamCdrOut.io.axis - assert( ~(upStreamCdrIn.io.axis.valid & ~upStreamCdrIn.io.axis.ready) ) + + val UpRecvStateIdle = 0.U + val UpRecvStateOHead = 1.U + val UpRecvStateFData = 2.U + val UpRecvStateCRC = 3.U + + val UpSendStateIdle = 0.U + val UpSendStateNHead = 1.U + val UpSendStateSHead = 2.U + val UpSendStateFData = 3.U + + val upOldHead = Reg( new Header_Info_Bundle ) + val upNewHead = Reg( new Header_Info_Bundle ) + + val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) ) //4 is reserve + + val upRecvSteteNext = Wire( UInt(3.W) ) + val upRecvStateCurr = RegNext( upRecvSteteNext, 0.U ) + + val upRecvCnt = Reg(UInt(10.W)) + val upSendCnt = Reg(UInt(10.W)) + + upRecvSteteNext := Mux1H(Seq( + (upRecvStateCurr === UpRecvStateIdle ) -> Mux( upStreamCdrIn.io.axis.valid, UpRecvStateOHead, UpRecvStateIdle ), + (upRecvStateCurr === UpRecvStateOHead) -> Mux( upStreamCdrIn.io.axis.fire, Mux( ~upStreamCdrIn.io.axis.bits.tlast, Mux( upRecvCnt === ((headByte)-1).U, UpRecvStateFData, UpRecvStateOHead), UpRecvStateIdle), UpRecvStateOHead ), + (upRecvStateCurr === UpRecvStateFData) -> Mux( upStreamCdrIn.io.axis.fire, Mux( ~upStreamCdrIn.io.axis.bits.tlast, Mux( upRecvCnt === (upOldHead.length - 1.U), UpRecvStateCRC, UpRecvStateFData), UpRecvStateIdle), UpRecvStateFData ), + (upRecvStateCurr === UpRecvStateCRC ) -> Mux( upStreamCdrIn.io.axis.fire & upStreamCdrIn.io.axis.bits.tlast, UpRecvStateIdle, UpRecvStateCRC ), + )) + + when( upRecvStateCurr =/= upRecvSteteNext){ + upRecvCnt := 0.U + } .elsewhen( upStreamCdrIn.io.axis.fire ){ + upRecvCnt := upRecvCnt + 1.U + } + + + + + + + + + + + + + + + + + + + +// val selfDataByte = Mux1H(Seq( +// (downOldHead.operator === 0.U) -> OpInitByte, +// (downOldHead.operator === 1.U) -> OpBoardCastByte, +// (downOldHead.operator === 2.U) -> OpUniCastByte, +// )) + +// val isDownStreamError = RegInit( false.B ) + +// val forwardDataByte = downNewHead.length + + +// when( downRecvStateCurr =/= downRecvSteteNext ){ +// downRecvCnt := 0.U +// } .elsewhen( downStreamCdrIn.io.axis.fire ){ +// downRecvCnt := downRecvCnt + 1.U +// } + +// //--------------- + +// when( downRecvStateCurr === DownRecvStateOHead & downStreamCdrIn.io.axis.fire ){ +// downOldHead := Cat( downOldHead.asUInt.tail(8), downStreamCdrIn.io.axis.tdata ).asTypeOf(Header_Info_Bundle) +// } + + +// //--------------- +// val isNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍 +// when( isNewHeadCreated ){ +// downNewHead.length := Mux( downOldHead.length >= selfDataByte, downOldHead.length - selfDataByte, 0.U ) +// downNewHead.operator := downOldHead.operator +// downNewHead.param := downOldHead.param +// } + + +// when( downRecvStateCurr === DownRecvStateSData & downStreamCdrIn.io.axis.fire ){ +// downRegTemp(downRecvCnt) := downStreamCdrIn.io.axis.tdata +// } + +// //--------------- +// downStreamFifo.io.enq.valid := +// downRecvStateCurr === DownRecvStateFData & downStreamCdrIn.io.axis.valid +// downStreamFifo.io.enq.bits.tdata := downStreamCdrIn.io.axis.bits.tdata +// downStreamFifo.io.enq.bits.tuser := downStreamCdrIn.io.axis.bits.tuser +// downStreamFifo.io.enq.bits.tlast := downRecvCnt === (forwardDataByte -1.U) | downStreamCdrIn.io.axis.bits.tlast + +// downStreamCdrIn.io.axis.ready := +// (downRecvStateCurr === DownRecvStateOHead) | +// (downRecvStateCurr === DownRecvStateSData) | +// (downRecvStateCurr === DownRecvStateFData) | +// (downRecvStateCurr === DownRecvStateCRC ) + +// when( downRecvStateCurr === DownRecvStateIdle & downRecvSteteNext === DownRecvStateOHead){ +// isDownStreamError := false.B +// } .elsewhen( downStreamFifo.io.enq.fire & downStreamFifo.io.enq.bits.tuser ){ +// isDownStreamError := true.B +// printf("Warning, Wrong Package Received, That could not happened!\n") +// } .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateOHead ){ +// isDownStreamError := true.B +// printf("Warning, Wrong Package Received, That could not happened!\n") +// } .elsewhen( downRecvStateCurr === DownRecvStateSHead & downRecvSteteNext === DownRecvStateOHead ){ +// isDownStreamError := true.B +// printf("Warning, Wrong Package Received, That could not happened!\n") +// } .elsewhen( downRecvStateCurr === DownRecvStateFHead & downRecvSteteNext === DownRecvStateOHead ){ +// isDownStreamError := true.B +// printf("Warning, Wrong Package Received, That could not happened!\n") +// } .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){ +// isDownStreamError := true.B +// printf("Warning, Wrong Package Received, That could not happened!\n") +// } + + + +// assert( ~(downRecvStateCurr === DownRecvStateFData & ~downStreamFifo.io.enq.ready), "Assert Failed, downStream Forward Fifo is OverFlow!" ) + + + + + + + + + + + + + + + + }