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参数化cdrInSample，支持4相位

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This commit is contained in:
RuigeLee
2025-09-11 18:57:58 +08:00
parent 99b9d9a72f
commit 958987ff6d
5 changed files with 70 additions and 87 deletions
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3
Makefile
View File

@@ -18,6 +18,7 @@ endif
shin: shin:
rm -f ./generated/shin/* rm -f ./generated/shin/*
rm -f ./generated/SimCDR/*
sbt "test:runMain test.testShinModule" sbt "test:runMain test.testShinModule"
testShin: testShin:
@@ -65,10 +66,8 @@ testShinClk:
testCDR: testCDR:
iverilog -Wall \ iverilog -Wall \
-o ./tb/build/simCDR.iverilog \ -o ./tb/build/simCDR.iverilog \
-y ./generated/shin \
-y ./generated/SimCDR \ -y ./generated/SimCDR \
-I ./generated/SimCDR \ -I ./generated/SimCDR \
-I ./generated/shin \
-D RANDOMIZE_REG_INIT \ -D RANDOMIZE_REG_INIT \
-D IVERILOG_COMPILE \ -D IVERILOG_COMPILE \
./tb/shinTest/SimCDRTb.v ./tb/shinTest/SimCDRTb.v

90
src/main/scala/backBoard/shin/CDRIn.scala
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@@ -11,10 +11,10 @@ class CDRInSampleIO extends Bundle{
} }
class CDRInMultiSample extends Module with RequireAsyncReset{ class CDRInMultiSample(clkNum: Int) extends Module with RequireAsyncReset{
require( clkNum == 16 || clkNum == 4 )
val io: CDRInSampleIO = IO(new CDRInSampleIO) val io: CDRInSampleIO = IO(new CDRInSampleIO)
val clkNum: Int = 16
require( clkNum == 16 )
//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先 //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
val multiCLK = IO(Input(Vec(clkNum, Bool()))) val multiCLK = IO(Input(Vec(clkNum, Bool())))
@@ -35,41 +35,12 @@ class CDRInMultiSample extends Module with RequireAsyncReset{
val sampleReg_Align = Wire(Vec(8*clkNum,Bool())) val sampleReg_Align = Wire(Vec(8*clkNum,Bool()))
dontTouch(sampleReg_Align) dontTouch(sampleReg_Align)
( 0 until 8 ).map{ gp =>
for( i <- 0 until clkNum ){ for( i <- gp*clkNum until (gp+1)*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i)(7) sampleReg_Align(i) := sampleReg_sync(i - gp*clkNum)(8-1-gp)
}
} }
for( i <- clkNum until 2*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-clkNum)(6)
}
for( i <- 2*clkNum until 3*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-2*clkNum)(5)
}
for( i <- 3*clkNum until 4*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-3*clkNum)(4)
}
for( i <- 4*clkNum until 5*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-4*clkNum)(3)
}
for( i <- 5*clkNum until 6*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-5*clkNum)(2)
}
for( i <- 6*clkNum until 7*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-6*clkNum)(1)
}
for( i <- 7*clkNum until 8*clkNum ){
sampleReg_Align(i) := sampleReg_sync(i-7*clkNum)(0)
}
val flitReg = val flitReg =
for( i <- 1 until (8*clkNum)-1 ) yield { for( i <- 1 until (8*clkNum)-1 ) yield {
@@ -102,48 +73,57 @@ class CDRInMultiSample extends Module with RequireAsyncReset{
val checkWindow = Wire( Vec(6, Bool()) ) val checkWindow = Wire( Vec(6, Bool()) )
dontTouch(checkWindow) dontTouch(checkWindow)
val lastPhase = 8*clkNum -2 - clkNum/2
checkWindow(0) := checkWindow(0) :=
Mux1H( (0 until 116).map{ i => Mux1H( (0 until lastPhase-2).map{ i =>
(arbCali === (i+2).U) -> flitReg(i) (arbCali === (i+2).U) -> flitReg(i)
}) })
checkWindow(1) := checkWindow(1) :=
Mux1H( (1 until 117).map{ i => Mux1H( (1 until lastPhase-1).map{ i =>
(arbCali === (i+1).U) -> flitReg(i) (arbCali === (i+1).U) -> flitReg(i)
}) })
checkWindow(2) := checkWindow(2) :=
Mux1H( (2 until 118).map{ i => Mux1H( (2 until lastPhase).map{ i =>
(arbCali === i.U) -> flitReg(i) (arbCali === i.U) -> flitReg(i)
}) })
checkWindow(3) := checkWindow(3) :=
Mux1H( (3 until 119).map{ i => Mux1H( (3 until lastPhase+1).map{ i =>
(arbCali === (i-1).U) -> flitReg(i) (arbCali === (i-1).U) -> flitReg(i)
}) })
checkWindow(4) := checkWindow(4) :=
Mux1H( (4 until 120).map{ i => Mux1H( (4 until lastPhase+2).map{ i =>
(arbCali === (i-2).U) -> flitReg(i) (arbCali === (i-2).U) -> flitReg(i)
}) })
checkWindow(5) := checkWindow(5) := (
Mux1H( (5 until 121).map{ i => if( clkNum == 16 ){
(arbCali === (i-3).U) -> flitReg(i) Mux1H( (5 until lastPhase+3).map{ i =>
}) (arbCali === (i-3).U) -> flitReg(i)
})
} else{
false.B
}
)
when( ~isLock ){ when( ~isLock ){
for( i <- 0 until 16 ){ for( i <- 0 until clkNum ){
val j = 50+16 - i - 1 val j = ((8/2)*clkNum-clkNum/2)+clkNum - i - 1
when( flitReg(j) ^ flitReg(j+1) ){ when( flitReg(j) ^ flitReg(j+1) ){
arbCali := j.U arbCali := j.U
} }
} }
}.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位 }.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位
assert( arbCali >= 2.U && arbCali < 118.U ) assert( arbCali >= 2.U && arbCali < lastPhase.U )
when( when(
(checkWindow(0) ^ checkWindow(1)) | (if( clkNum == 16 ) { (checkWindow(0) ^ checkWindow(1)) } else {false.B}) |
(checkWindow(1) ^ checkWindow(2)) (checkWindow(1) ^ checkWindow(2))
){ ){
when( arbCali =/= 2.U ){ when( arbCali =/= 2.U ){
@@ -151,17 +131,17 @@ class CDRInMultiSample extends Module with RequireAsyncReset{
} }
} .elsewhen( } .elsewhen(
(checkWindow(3) ^ checkWindow(4)) | (checkWindow(3) ^ checkWindow(4)) |
(checkWindow(4) ^ checkWindow(5)) (if( clkNum == 16 ) { (checkWindow(4) ^ checkWindow(5)) } else {false.B})
){ ){
when( arbCali =/= 117.U ){ when( arbCali =/= (lastPhase-1).U ){
arbCali := arbCali + 1.U arbCali := arbCali + 1.U
} }
} }
} }
when( ~isLock ){ when( ~isLock ){
for( i <- 0 until 16 ){ for( i <- 0 until clkNum ){
val j = 50+16 - i - 1 val j = ((8/2)*clkNum-clkNum/2)+clkNum - i - 1
when( flitReg(j) ^ flitReg(j+1) ){ when( flitReg(j) ^ flitReg(j+1) ){
isLock := true.B isLock := true.B
} }
@@ -173,8 +153,8 @@ class CDRInMultiSample extends Module with RequireAsyncReset{
val asyncSerDat = val asyncSerDat =
Mux1H( Mux1H(
(for { i <- 2 until 118 } yield { (for { i <- 2 until lastPhase } yield {
(arbCali === i.U) -> flitReg(i+(8)) (arbCali === i.U) -> flitReg(i+(clkNum/2))
}) })
) )

16
src/main/scala/backBoard/shin/ShinTop.scala
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@@ -19,8 +19,8 @@ class ShinTop extends Module with RequireAsyncReset{
{ {
val downCDRInSampleA = Module(new CDRInMultiSample) val downCDRInSampleA = Module(new CDRInMultiSample(clkNum = 16))
val upCDRInSampleA = Module(new CDRInMultiSample) val upCDRInSampleA = Module(new CDRInMultiSample(clkNum = 16))
downCDRInSampleA.multiCLK := io.multiCLK downCDRInSampleA.multiCLK := io.multiCLK
upCDRInSampleA.multiCLK := io.multiCLK upCDRInSampleA.multiCLK := io.multiCLK
@@ -30,19 +30,19 @@ class ShinTop extends Module with RequireAsyncReset{
} }
{ {
val downCDRInSampleB = Module(new CDRInMultiSample) val downCDRInSampleB = Module(new CDRInMultiSample(clkNum = 4))
val upCDRInSampleB = Module(new CDRInMultiSample) val upCDRInSampleB = Module(new CDRInMultiSample(clkNum = 4))
downCDRInSampleB.multiCLK := io.multiCLK downCDRInSampleB.multiCLK := io.multiCLKDiv4
upCDRInSampleB.multiCLK := io.multiCLK upCDRInSampleB.multiCLK := io.multiCLKDiv4
downCDRInSampleB.io <> mstSlvSwitch.io.downCDRSampleIn(1) downCDRInSampleB.io <> mstSlvSwitch.io.downCDRSampleIn(1)
upCDRInSampleB.io <> mstSlvSwitch.io.upCDRSampleIn(1) upCDRInSampleB.io <> mstSlvSwitch.io.upCDRSampleIn(1)
} }
{ {
val downCDRInSampleC = Module(new CDRInMultiSample) val downCDRInSampleC = Module(new CDRInMultiSample(clkNum = 16))
val upCDRInSampleC = Module(new CDRInMultiSample) val upCDRInSampleC = Module(new CDRInMultiSample(clkNum = 16))
downCDRInSampleC.multiCLK := io.multiCLK downCDRInSampleC.multiCLK := io.multiCLK
upCDRInSampleC.multiCLK := io.multiCLK upCDRInSampleC.multiCLK := io.multiCLK

40
src/test/scala/SimCDR.scala
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@@ -21,7 +21,7 @@ class SimCDR extends Module with RequireAsyncReset{
val cdrInAxis = Module(new CDRInAxis) val cdrInAxis = Module(new CDRInAxis)
val cdrInSample = Module(new CDRInMultiSample) val cdrInSample = Module(new CDRInMultiSample(clkNum = 4))
val cdrOut = Module(new CDROut) val cdrOut = Module(new CDROut)
val record = Module( new Queue(UInt(8.W), 256) ) val record = Module( new Queue(UInt(8.W), 256) )
@@ -57,7 +57,11 @@ class SimCDR extends Module with RequireAsyncReset{
cdrInAxis.clock := io.multiCLK(0).asClock cdrInAxis.clock := io.multiCLK(0).asClock
cdrInSample.clock := io.multiCLK(0).asClock cdrInSample.clock := io.multiCLK(0).asClock
cdrInAxis.io.flush := io.flush cdrInAxis.io.flush := io.flush
cdrInSample.multiCLK := io.multiCLK // cdrInSample.multiCLK := io.multiCLK
cdrInSample.multiCLK(0) := io.multiCLK(0)
cdrInSample.multiCLK(1) := io.multiCLK(4)
cdrInSample.multiCLK(2) := io.multiCLK(8)
cdrInSample.multiCLK(3) := io.multiCLK(12)
cdrInAxis.io.syncSerDat := cdrInSample.io.syncSerDat cdrInAxis.io.syncSerDat := cdrInSample.io.syncSerDat
@@ -87,7 +91,7 @@ class SimCDR extends Module with RequireAsyncReset{
val isUsing8b10b = false.B val isUsing8b10b = true.B
when( isUsing8b10b ){ when( isUsing8b10b ){
@@ -107,28 +111,28 @@ class SimCDR extends Module with RequireAsyncReset{
} }
// val coverData = RegInit(VecInit(Seq.fill(512){false.B})) val coverData = RegInit(VecInit(Seq.fill(512){false.B}))
// when( record.io.enq.fire ){
// for( i <- 0 until 256 ){
// when( record.io.enq.bits === i.U ){
// when( b8b10Encoder.rdTest ){
// coverData(i) := true.B
// } .otherwise{
// coverData(256+i) := true.B
// }
// }
// }
// }
val coverData = RegInit(VecInit(Seq.fill(256){false.B}))
when( record.io.enq.fire ){ when( record.io.enq.fire ){
for( i <- 0 until 256 ){ for( i <- 0 until 256 ){
when( record.io.enq.bits === i.U ){ when( record.io.enq.bits === i.U ){
coverData(i) := true.B when( b8b10Encoder.rdTest ){
coverData(i) := true.B
} .otherwise{
coverData(256+i) := true.B
}
} }
} }
} }
// val coverData = RegInit(VecInit(Seq.fill(256){false.B}))
// when( record.io.enq.fire ){
// for( i <- 0 until 256 ){
// when( record.io.enq.bits === i.U ){
// coverData(i) := true.B
// }
// }
// }
val coverage = PopCount(coverData.asUInt) val coverage = PopCount(coverData.asUInt)
when( io.isSuccess ){ when( io.isSuccess ){
printf( cf"Coverage: ${coverage}\n") printf( cf"Coverage: ${coverage}\n")

8
tb/shinTest/SimCDRTb.v
View File

@@ -23,7 +23,7 @@ module SimCDRTb(
initial begin initial begin
forever begin #80 clock <= ~clock; end forever begin #8000000 clock <= ~clock; end
end end
generate generate
@@ -31,10 +31,10 @@ module SimCDRTb(
initial begin initial begin
multiCLK[i] = 0; multiCLK[i] = 0;
for( integer j = 0; j < i; j = j + 1 ) begin for( integer j = 0; j < i; j = j + 1 ) begin
#20 #1000176
; ;
end end
forever begin #80 multiCLK[i] <= ~multiCLK[i]; end forever begin #8001408 multiCLK[i] <= ~multiCLK[i]; end
end end
end end
endgenerate endgenerate
@@ -43,7 +43,7 @@ module SimCDRTb(
wire success; wire success;
wire failed; wire failed;
integer seed = 666; integer seed = 606;
always @(posedge clock) begin always @(posedge clock) begin
data <= $random(seed); data <= $random(seed);
end end