diff --git a/Makefile b/Makefile index cd81313..3a2860c 100644 --- a/Makefile +++ b/Makefile @@ -18,6 +18,7 @@ endif shin: rm -f ./generated/shin/* + rm -f ./generated/SimCDR/* sbt "test:runMain test.testShinModule" testShin: @@ -65,10 +66,8 @@ testShinClk: testCDR: iverilog -Wall \ -o ./tb/build/simCDR.iverilog \ - -y ./generated/shin \ -y ./generated/SimCDR \ -I ./generated/SimCDR \ - -I ./generated/shin \ -D RANDOMIZE_REG_INIT \ -D IVERILOG_COMPILE \ ./tb/shinTest/SimCDRTb.v diff --git a/src/main/scala/backBoard/shin/CDRIn.scala b/src/main/scala/backBoard/shin/CDRIn.scala index ee91f76..18f3d8d 100644 --- a/src/main/scala/backBoard/shin/CDRIn.scala +++ b/src/main/scala/backBoard/shin/CDRIn.scala @@ -11,10 +11,10 @@ class CDRInSampleIO extends Bundle{ } -class CDRInMultiSample extends Module with RequireAsyncReset{ +class CDRInMultiSample(clkNum: Int) extends Module with RequireAsyncReset{ + require( clkNum == 16 || clkNum == 4 ) val io: CDRInSampleIO = IO(new CDRInSampleIO) - val clkNum: Int = 16 - require( clkNum == 16 ) + //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先 val multiCLK = IO(Input(Vec(clkNum, Bool()))) @@ -35,41 +35,12 @@ class CDRInMultiSample extends Module with RequireAsyncReset{ val sampleReg_Align = Wire(Vec(8*clkNum,Bool())) dontTouch(sampleReg_Align) - - for( i <- 0 until clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i)(7) + ( 0 until 8 ).map{ gp => + for( i <- gp*clkNum until (gp+1)*clkNum ){ + sampleReg_Align(i) := sampleReg_sync(i - gp*clkNum)(8-1-gp) + } } - for( i <- clkNum until 2*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-clkNum)(6) - } - - for( i <- 2*clkNum until 3*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-2*clkNum)(5) - } - - for( i <- 3*clkNum until 4*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-3*clkNum)(4) - } - - for( i <- 4*clkNum until 5*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-4*clkNum)(3) - } - - for( i <- 5*clkNum until 6*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-5*clkNum)(2) - } - - for( i <- 6*clkNum until 7*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-6*clkNum)(1) - } - - for( i <- 7*clkNum until 8*clkNum ){ - sampleReg_Align(i) := sampleReg_sync(i-7*clkNum)(0) - } - - - val flitReg = for( i <- 1 until (8*clkNum)-1 ) yield { @@ -102,48 +73,57 @@ class CDRInMultiSample extends Module with RequireAsyncReset{ val checkWindow = Wire( Vec(6, Bool()) ) dontTouch(checkWindow) + val lastPhase = 8*clkNum -2 - clkNum/2 + checkWindow(0) := - Mux1H( (0 until 116).map{ i => + Mux1H( (0 until lastPhase-2).map{ i => (arbCali === (i+2).U) -> flitReg(i) }) checkWindow(1) := - Mux1H( (1 until 117).map{ i => + Mux1H( (1 until lastPhase-1).map{ i => (arbCali === (i+1).U) -> flitReg(i) }) checkWindow(2) := - Mux1H( (2 until 118).map{ i => + Mux1H( (2 until lastPhase).map{ i => (arbCali === i.U) -> flitReg(i) }) checkWindow(3) := - Mux1H( (3 until 119).map{ i => + Mux1H( (3 until lastPhase+1).map{ i => (arbCali === (i-1).U) -> flitReg(i) }) checkWindow(4) := - Mux1H( (4 until 120).map{ i => + Mux1H( (4 until lastPhase+2).map{ i => (arbCali === (i-2).U) -> flitReg(i) }) - checkWindow(5) := - Mux1H( (5 until 121).map{ i => - (arbCali === (i-3).U) -> flitReg(i) - }) + checkWindow(5) := ( + if( clkNum == 16 ){ + Mux1H( (5 until lastPhase+3).map{ i => + (arbCali === (i-3).U) -> flitReg(i) + }) + } else{ + false.B + } + ) + + when( ~isLock ){ - for( i <- 0 until 16 ){ - val j = 50+16 - i - 1 + for( i <- 0 until clkNum ){ + val j = ((8/2)*clkNum-clkNum/2)+clkNum - i - 1 when( flitReg(j) ^ flitReg(j+1) ){ arbCali := j.U } } }.elsewhen( checkCnt.andR ){ //锁定之后，只允许每16cycle移动一相位 - assert( arbCali >= 2.U && arbCali < 118.U ) + assert( arbCali >= 2.U && arbCali < lastPhase.U ) when( - (checkWindow(0) ^ checkWindow(1)) | + (if( clkNum == 16 ) { (checkWindow(0) ^ checkWindow(1)) } else {false.B}) | (checkWindow(1) ^ checkWindow(2)) ){ when( arbCali =/= 2.U ){ @@ -151,17 +131,17 @@ class CDRInMultiSample extends Module with RequireAsyncReset{ } } .elsewhen( (checkWindow(3) ^ checkWindow(4)) | - (checkWindow(4) ^ checkWindow(5)) + (if( clkNum == 16 ) { (checkWindow(4) ^ checkWindow(5)) } else {false.B}) ){ - when( arbCali =/= 117.U ){ + when( arbCali =/= (lastPhase-1).U ){ arbCali := arbCali + 1.U } } } when( ~isLock ){ - for( i <- 0 until 16 ){ - val j = 50+16 - i - 1 + for( i <- 0 until clkNum ){ + val j = ((8/2)*clkNum-clkNum/2)+clkNum - i - 1 when( flitReg(j) ^ flitReg(j+1) ){ isLock := true.B } @@ -173,8 +153,8 @@ class CDRInMultiSample extends Module with RequireAsyncReset{ val asyncSerDat = Mux1H( - (for { i <- 2 until 118 } yield { - (arbCali === i.U) -> flitReg(i+(8)) + (for { i <- 2 until lastPhase } yield { + (arbCali === i.U) -> flitReg(i+(clkNum/2)) }) ) diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index a26f442..6281bb6 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -19,8 +19,8 @@ class ShinTop extends Module with RequireAsyncReset{ { - val downCDRInSampleA = Module(new CDRInMultiSample) - val upCDRInSampleA = Module(new CDRInMultiSample) + val downCDRInSampleA = Module(new CDRInMultiSample(clkNum = 16)) + val upCDRInSampleA = Module(new CDRInMultiSample(clkNum = 16)) downCDRInSampleA.multiCLK := io.multiCLK upCDRInSampleA.multiCLK := io.multiCLK @@ -30,19 +30,19 @@ class ShinTop extends Module with RequireAsyncReset{ } { - val downCDRInSampleB = Module(new CDRInMultiSample) - val upCDRInSampleB = Module(new CDRInMultiSample) + val downCDRInSampleB = Module(new CDRInMultiSample(clkNum = 4)) + val upCDRInSampleB = Module(new CDRInMultiSample(clkNum = 4)) - downCDRInSampleB.multiCLK := io.multiCLK - upCDRInSampleB.multiCLK := io.multiCLK + downCDRInSampleB.multiCLK := io.multiCLKDiv4 + upCDRInSampleB.multiCLK := io.multiCLKDiv4 downCDRInSampleB.io <> mstSlvSwitch.io.downCDRSampleIn(1) upCDRInSampleB.io <> mstSlvSwitch.io.upCDRSampleIn(1) } { - val downCDRInSampleC = Module(new CDRInMultiSample) - val upCDRInSampleC = Module(new CDRInMultiSample) + val downCDRInSampleC = Module(new CDRInMultiSample(clkNum = 16)) + val upCDRInSampleC = Module(new CDRInMultiSample(clkNum = 16)) downCDRInSampleC.multiCLK := io.multiCLK upCDRInSampleC.multiCLK := io.multiCLK diff --git a/src/test/scala/SimCDR.scala b/src/test/scala/SimCDR.scala index 4f46fec..9885a30 100644 --- a/src/test/scala/SimCDR.scala +++ b/src/test/scala/SimCDR.scala @@ -21,7 +21,7 @@ class SimCDR extends Module with RequireAsyncReset{ val cdrInAxis = Module(new CDRInAxis) - val cdrInSample = Module(new CDRInMultiSample) + val cdrInSample = Module(new CDRInMultiSample(clkNum = 4)) val cdrOut = Module(new CDROut) val record = Module( new Queue(UInt(8.W), 256) ) @@ -57,7 +57,11 @@ class SimCDR extends Module with RequireAsyncReset{ cdrInAxis.clock := io.multiCLK(0).asClock cdrInSample.clock := io.multiCLK(0).asClock cdrInAxis.io.flush := io.flush - cdrInSample.multiCLK := io.multiCLK + // cdrInSample.multiCLK := io.multiCLK + cdrInSample.multiCLK(0) := io.multiCLK(0) + cdrInSample.multiCLK(1) := io.multiCLK(4) + cdrInSample.multiCLK(2) := io.multiCLK(8) + cdrInSample.multiCLK(3) := io.multiCLK(12) cdrInAxis.io.syncSerDat := cdrInSample.io.syncSerDat @@ -87,7 +91,7 @@ class SimCDR extends Module with RequireAsyncReset{ - val isUsing8b10b = false.B + val isUsing8b10b = true.B when( isUsing8b10b ){ @@ -107,28 +111,28 @@ class SimCDR extends Module with RequireAsyncReset{ } - // val coverData = RegInit(VecInit(Seq.fill(512){false.B})) - // when( record.io.enq.fire ){ - // for( i <- 0 until 256 ){ - // when( record.io.enq.bits === i.U ){ - // when( b8b10Encoder.rdTest ){ - // coverData(i) := true.B - // } .otherwise{ - // coverData(256+i) := true.B - // } - // } - // } - // } - - val coverData = RegInit(VecInit(Seq.fill(256){false.B})) + val coverData = RegInit(VecInit(Seq.fill(512){false.B})) when( record.io.enq.fire ){ for( i <- 0 until 256 ){ when( record.io.enq.bits === i.U ){ - coverData(i) := true.B + when( b8b10Encoder.rdTest ){ + coverData(i) := true.B + } .otherwise{ + coverData(256+i) := true.B + } } } } + // val coverData = RegInit(VecInit(Seq.fill(256){false.B})) + // when( record.io.enq.fire ){ + // for( i <- 0 until 256 ){ + // when( record.io.enq.bits === i.U ){ + // coverData(i) := true.B + // } + // } + // } + val coverage = PopCount(coverData.asUInt) when( io.isSuccess ){ printf( cf"Coverage: ${coverage}\n") diff --git a/tb/shinTest/SimCDRTb.v b/tb/shinTest/SimCDRTb.v index dc818d6..b8541a0 100644 --- a/tb/shinTest/SimCDRTb.v +++ b/tb/shinTest/SimCDRTb.v @@ -23,7 +23,7 @@ module SimCDRTb( initial begin - forever begin #80 clock <= ~clock; end + forever begin #8000000 clock <= ~clock; end end generate @@ -31,10 +31,10 @@ module SimCDRTb( initial begin multiCLK[i] = 0; for( integer j = 0; j < i; j = j + 1 ) begin - #20 + #1000176 ; end - forever begin #80 multiCLK[i] <= ~multiCLK[i]; end + forever begin #8001408 multiCLK[i] <= ~multiCLK[i]; end end end endgenerate @@ -43,7 +43,7 @@ module SimCDRTb( wire success; wire failed; - integer seed = 666; + integer seed = 606; always @(posedge clock) begin data <= $random(seed); end