参数化cdrInSample，支持4相位

tb/shinTest/SimCDRTb.v

@@ -23,7 +23,7 @@ module SimCDRTb(
 
 
     initial begin
-        forever begin #80 clock <= ~clock; end
+        forever begin #8000000 clock <= ~clock; end
     end
 
     generate
@@ -31,10 +31,10 @@ module SimCDRTb(
         initial begin
         multiCLK[i] = 0;
         for( integer j = 0; j < i; j = j + 1 ) begin
-            #20
+            #1000176
             ;
         end
-        forever begin #80 multiCLK[i] <= ~multiCLK[i]; end
+        forever begin #8001408 multiCLK[i] <= ~multiCLK[i]; end
         end
     end  
     endgenerate
@@ -43,7 +43,7 @@ module SimCDRTb(
     wire success;
     wire failed;
 
-    integer seed = 666;
+    integer seed = 606;
     always @(posedge clock) begin
         data <= $random(seed);
     end