参数化cdrInSample,支持4相位
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@@ -21,7 +21,7 @@ class SimCDR extends Module with RequireAsyncReset{
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val cdrInAxis = Module(new CDRInAxis)
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val cdrInSample = Module(new CDRInMultiSample)
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val cdrInSample = Module(new CDRInMultiSample(clkNum = 4))
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val cdrOut = Module(new CDROut)
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val record = Module( new Queue(UInt(8.W), 256) )
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@@ -57,7 +57,11 @@ class SimCDR extends Module with RequireAsyncReset{
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cdrInAxis.clock := io.multiCLK(0).asClock
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cdrInSample.clock := io.multiCLK(0).asClock
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cdrInAxis.io.flush := io.flush
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cdrInSample.multiCLK := io.multiCLK
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// cdrInSample.multiCLK := io.multiCLK
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cdrInSample.multiCLK(0) := io.multiCLK(0)
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cdrInSample.multiCLK(1) := io.multiCLK(4)
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cdrInSample.multiCLK(2) := io.multiCLK(8)
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cdrInSample.multiCLK(3) := io.multiCLK(12)
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cdrInAxis.io.syncSerDat := cdrInSample.io.syncSerDat
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@@ -87,7 +91,7 @@ class SimCDR extends Module with RequireAsyncReset{
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val isUsing8b10b = false.B
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val isUsing8b10b = true.B
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when( isUsing8b10b ){
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@@ -107,28 +111,28 @@ class SimCDR extends Module with RequireAsyncReset{
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}
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// val coverData = RegInit(VecInit(Seq.fill(512){false.B}))
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// when( record.io.enq.fire ){
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// for( i <- 0 until 256 ){
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// when( record.io.enq.bits === i.U ){
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// when( b8b10Encoder.rdTest ){
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// coverData(i) := true.B
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// } .otherwise{
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// coverData(256+i) := true.B
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// }
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// }
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// }
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// }
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val coverData = RegInit(VecInit(Seq.fill(256){false.B}))
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val coverData = RegInit(VecInit(Seq.fill(512){false.B}))
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when( record.io.enq.fire ){
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for( i <- 0 until 256 ){
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when( record.io.enq.bits === i.U ){
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coverData(i) := true.B
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when( b8b10Encoder.rdTest ){
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coverData(i) := true.B
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} .otherwise{
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coverData(256+i) := true.B
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}
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}
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}
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}
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// val coverData = RegInit(VecInit(Seq.fill(256){false.B}))
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// when( record.io.enq.fire ){
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// for( i <- 0 until 256 ){
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// when( record.io.enq.bits === i.U ){
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// coverData(i) := true.B
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// }
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// }
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// }
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val coverage = PopCount(coverData.asUInt)
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when( io.isSuccess ){
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printf( cf"Coverage: ${coverage}\n")
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