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参数化cdrInSample，支持4相位

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This commit is contained in:
RuigeLee
2025-09-11 18:57:58 +08:00
parent 99b9d9a72f
commit 958987ff6d
5 changed files with 70 additions and 87 deletions
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16
src/main/scala/backBoard/shin/ShinTop.scala
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@@ -19,8 +19,8 @@ class ShinTop extends Module with RequireAsyncReset{
{
val downCDRInSampleA = Module(new CDRInMultiSample)
val upCDRInSampleA = Module(new CDRInMultiSample)
val downCDRInSampleA = Module(new CDRInMultiSample(clkNum = 16))
val upCDRInSampleA = Module(new CDRInMultiSample(clkNum = 16))
downCDRInSampleA.multiCLK := io.multiCLK
upCDRInSampleA.multiCLK := io.multiCLK
@@ -30,19 +30,19 @@ class ShinTop extends Module with RequireAsyncReset{
}
{
val downCDRInSampleB = Module(new CDRInMultiSample)
val upCDRInSampleB = Module(new CDRInMultiSample)
val downCDRInSampleB = Module(new CDRInMultiSample(clkNum = 4))
val upCDRInSampleB = Module(new CDRInMultiSample(clkNum = 4))
downCDRInSampleB.multiCLK := io.multiCLK
upCDRInSampleB.multiCLK := io.multiCLK
downCDRInSampleB.multiCLK := io.multiCLKDiv4
upCDRInSampleB.multiCLK := io.multiCLKDiv4
downCDRInSampleB.io <> mstSlvSwitch.io.downCDRSampleIn(1)
upCDRInSampleB.io <> mstSlvSwitch.io.upCDRSampleIn(1)
}
{
val downCDRInSampleC = Module(new CDRInMultiSample)
val upCDRInSampleC = Module(new CDRInMultiSample)
val downCDRInSampleC = Module(new CDRInMultiSample(clkNum = 16))
val upCDRInSampleC = Module(new CDRInMultiSample(clkNum = 16))
downCDRInSampleC.multiCLK := io.multiCLK
upCDRInSampleC.multiCLK := io.multiCLK