参数化cdrInSample，支持4相位

2025-09-11 18:57:58 +08:00
parent 99b9d9a72f
commit 958987ff6d
5 changed files with 70 additions and 87 deletions
--- a/3
+++ b/3
@@ -18,6 +18,7 @@ endif

 shin:
 	rm -f ./generated/shin/*
+	rm -f ./generated/SimCDR/*
 	sbt "test:runMain test.testShinModule"

 testShin:
@@ -65,10 +66,8 @@ testShinClk:
 testCDR:
 	iverilog -Wall  \
 	-o ./tb/build/simCDR.iverilog  \
-	-y ./generated/shin \
 	-y ./generated/SimCDR \
 	-I ./generated/SimCDR \
-	-I ./generated/shin \
 	-D RANDOMIZE_REG_INIT \
 	-D IVERILOG_COMPILE \
 	./tb/shinTest/SimCDRTb.v