对FSMC的外部IO仿真接线

Makefile

@@ -57,7 +57,6 @@ VSimTop:
 	+define+RANDOMIZE_INVALID_ASSIGN \
 	+define+RANDOMIZE_REG_INIT \
 	+define+RANDOMIZE_DELAY=0 \
-	+define+VERILATOR \
 	--exe --build \
 	${PWD}/tb/verilator/sim_main.cpp \
 	-Mdir ./tb/build/ \

src/main/scala/backBoard/ebus/FSMC2TileLink.scala

@@ -160,12 +160,10 @@ class FSMC2TileLink(implicit p: Parameters) extends LazyModule{
     val io = IO(new FSMC_Port_Bundle)
 
     val ( fsmc_bus, fsmc_edge ) = fsmcNode.in.head
-    // val tla = Wire(new DecoupledIO(new TLBundleA(fsmc_edge.bundle)))
-    // val tld = Wire(new DecoupledIO(new TLBundleD(fsmc_edge.bundle)))
 
     val sram  = Module(new MirrorSRAMDP())
-    //assert( ~(sram.io.enwA & sram.io.enrA) )
-    //assert( ~(sram.io.enwB & sram.io.enrB) )
+    assert( ~(sram.io.enwA & sram.io.enrA) )
+    assert( ~(sram.io.enwB & sram.io.enrB) )
     sram.io.clockA := clock.asBool //system
     sram.io.clockB := clock.asBool //system
 

src/main/scala/backBoard/ebus/TL2CDR.scala

@@ -9,30 +9,6 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.interrupts._
 
 
-// abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
-// abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
-
-// case object BackParamsKey extends Field[BackSetting]
-
-// case class BackSetting(
-// ){
-
-// }
-
-// trait HasBackParameters {
-//   implicit val p: Parameters
-
-//   val backSetting = p(BackParamsKey)
-// }
-
-
-
-// class BackCfg extends Config((_, _, _) => {
-//   case BackParamsKey => BackSetting()
-// })
-
-
-
 class TL2CDR(implicit p: Parameters) extends LazyModule{
   val device = new SimpleDevice("TL_CDR", Nil)
   val node = TLManagerNode(Seq(TLSlavePortParameters.v1(

tb/verilator/SimTop.v

@@ -211,7 +211,15 @@ ExampleRocketSystem s_rocket_mst(
   .cdrio_dDatIn(1'b0),
   .cdrio_dDatOut(dDatSer[0]),
   .cdrio_isOnline(),
-  .cdrio_isLast(1'b0)
+  .cdrio_isLast(1'b0),
+
+  .fsmcio_ADIn(16'b0),
+  .fsmcio_ADOut(),
+  .fsmcio_ADOEn(),
+  .fsmcio_csn(1'b1),
+  .fsmcio_rdn(1'b1),
+  .fsmcio_wrn(1'b1),
+  .fsmcio_advn(1'b1)
 );
 
 
@@ -397,7 +405,15 @@ ExampleRocketSystem s_rocket_slv0(
   .cdrio_dDatOut(dDatSer[1]),
 
   .cdrio_isOnline(),
-  .cdrio_isLast(1'b0)
+  .cdrio_isLast(1'b0),
+
+  .fsmcio_ADIn(16'b0),
+  .fsmcio_ADOut(),
+  .fsmcio_ADOEn(),
+  .fsmcio_csn(1'b1),
+  .fsmcio_rdn(1'b1),
+  .fsmcio_wrn(1'b1),
+  .fsmcio_advn(1'b1)
 );
 
 
@@ -583,7 +599,15 @@ ExampleRocketSystem s_rocket_slv1(
   .cdrio_dDatOut(dDatSer[2]),
 
   .cdrio_isOnline(),
-  .cdrio_isLast(1'b0)
+  .cdrio_isLast(1'b0),
+
+  .fsmcio_ADIn(16'b0),
+  .fsmcio_ADOut(),
+  .fsmcio_ADOEn(),
+  .fsmcio_csn(1'b1),
+  .fsmcio_rdn(1'b1),
+  .fsmcio_wrn(1'b1),
+  .fsmcio_advn(1'b1)
 );
 
 
@@ -769,7 +793,15 @@ ExampleRocketSystem s_rocket_slv2(
   .cdrio_dDatOut(),
 
   .cdrio_isOnline(),
-  .cdrio_isLast(1'b1)
+  .cdrio_isLast(1'b1),
+
+  .fsmcio_ADIn(16'b0),
+  .fsmcio_ADOut(),
+  .fsmcio_ADOEn(),
+  .fsmcio_csn(1'b1),
+  .fsmcio_rdn(1'b1),
+  .fsmcio_wrn(1'b1),
+  .fsmcio_advn(1'b1)
 );