From 94acbfae03896f5ea8edfe2b6dfcbd23f3967431 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Mon, 10 Feb 2025 11:17:39 +0800
Subject: [PATCH] =?UTF-8?q?=E5=AF=B9FSMC=E7=9A=84=E5=A4=96=E9=83=A8IO?=
 =?UTF-8?q?=E4=BB=BF=E7=9C=9F=E6=8E=A5=E7=BA=BF?=
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---
 Makefile                                      |  1 -
 .../scala/backBoard/ebus/FSMC2TileLink.scala  |  6 +--
 src/main/scala/backBoard/ebus/TL2CDR.scala    | 24 -----------
 tb/verilator/SimTop.v                         | 40 +++++++++++++++++--
 4 files changed, 38 insertions(+), 33 deletions(-)

diff --git a/Makefile b/Makefile
index 2c6dcb2..4fbfeb2 100644
--- a/Makefile
+++ b/Makefile
@@ -57,7 +57,6 @@ VSimTop:
 	+define+RANDOMIZE_INVALID_ASSIGN \
 	+define+RANDOMIZE_REG_INIT \
 	+define+RANDOMIZE_DELAY=0 \
-	+define+VERILATOR \
 	--exe --build \
 	${PWD}/tb/verilator/sim_main.cpp \
 	-Mdir ./tb/build/ \
diff --git a/src/main/scala/backBoard/ebus/FSMC2TileLink.scala b/src/main/scala/backBoard/ebus/FSMC2TileLink.scala
index 10179ea..d14b1b4 100644
--- a/src/main/scala/backBoard/ebus/FSMC2TileLink.scala
+++ b/src/main/scala/backBoard/ebus/FSMC2TileLink.scala
@@ -160,12 +160,10 @@ class FSMC2TileLink(implicit p: Parameters) extends LazyModule{
     val io = IO(new FSMC_Port_Bundle)
 
     val ( fsmc_bus, fsmc_edge ) = fsmcNode.in.head
-    // val tla = Wire(new DecoupledIO(new TLBundleA(fsmc_edge.bundle)))
-    // val tld = Wire(new DecoupledIO(new TLBundleD(fsmc_edge.bundle)))
 
     val sram  = Module(new MirrorSRAMDP())
-    //assert( ~(sram.io.enwA & sram.io.enrA) )
-    //assert( ~(sram.io.enwB & sram.io.enrB) )
+    assert( ~(sram.io.enwA & sram.io.enrA) )
+    assert( ~(sram.io.enwB & sram.io.enrB) )
     sram.io.clockA := clock.asBool //system
     sram.io.clockB := clock.asBool //system
 
diff --git a/src/main/scala/backBoard/ebus/TL2CDR.scala b/src/main/scala/backBoard/ebus/TL2CDR.scala
index ae7e887..73811af 100644
--- a/src/main/scala/backBoard/ebus/TL2CDR.scala
+++ b/src/main/scala/backBoard/ebus/TL2CDR.scala
@@ -9,30 +9,6 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.interrupts._
 
 
-// abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
-// abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
-
-// case object BackParamsKey extends Field[BackSetting]
-
-// case class BackSetting(
-// ){
-
-// }
-
-// trait HasBackParameters {
-//   implicit val p: Parameters
-
-//   val backSetting = p(BackParamsKey)
-// }
-
-
-
-// class BackCfg extends Config((_, _, _) => {
-//   case BackParamsKey => BackSetting()
-// })
-
-
-
 class TL2CDR(implicit p: Parameters) extends LazyModule{
   val device = new SimpleDevice("TL_CDR", Nil)
   val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
diff --git a/tb/verilator/SimTop.v b/tb/verilator/SimTop.v
index 3bb0639..e07f7c3 100644
--- a/tb/verilator/SimTop.v
+++ b/tb/verilator/SimTop.v
@@ -211,7 +211,15 @@ ExampleRocketSystem s_rocket_mst(
   .cdrio_dDatIn(1'b0),
   .cdrio_dDatOut(dDatSer[0]),
   .cdrio_isOnline(),
-  .cdrio_isLast(1'b0)
+  .cdrio_isLast(1'b0),
+
+  .fsmcio_ADIn(16'b0),
+  .fsmcio_ADOut(),
+  .fsmcio_ADOEn(),
+  .fsmcio_csn(1'b1),
+  .fsmcio_rdn(1'b1),
+  .fsmcio_wrn(1'b1),
+  .fsmcio_advn(1'b1)
 );
 
 
@@ -397,7 +405,15 @@ ExampleRocketSystem s_rocket_slv0(
   .cdrio_dDatOut(dDatSer[1]),
 
   .cdrio_isOnline(),
-  .cdrio_isLast(1'b0)
+  .cdrio_isLast(1'b0),
+
+  .fsmcio_ADIn(16'b0),
+  .fsmcio_ADOut(),
+  .fsmcio_ADOEn(),
+  .fsmcio_csn(1'b1),
+  .fsmcio_rdn(1'b1),
+  .fsmcio_wrn(1'b1),
+  .fsmcio_advn(1'b1)
 );
 
 
@@ -583,7 +599,15 @@ ExampleRocketSystem s_rocket_slv1(
   .cdrio_dDatOut(dDatSer[2]),
 
   .cdrio_isOnline(),
-  .cdrio_isLast(1'b0)
+  .cdrio_isLast(1'b0),
+
+  .fsmcio_ADIn(16'b0),
+  .fsmcio_ADOut(),
+  .fsmcio_ADOEn(),
+  .fsmcio_csn(1'b1),
+  .fsmcio_rdn(1'b1),
+  .fsmcio_wrn(1'b1),
+  .fsmcio_advn(1'b1)
 );
 
 
@@ -769,7 +793,15 @@ ExampleRocketSystem s_rocket_slv2(
   .cdrio_dDatOut(),
 
   .cdrio_isOnline(),
-  .cdrio_isLast(1'b1)
+  .cdrio_isLast(1'b1),
+
+  .fsmcio_ADIn(16'b0),
+  .fsmcio_ADOut(),
+  .fsmcio_ADOEn(),
+  .fsmcio_csn(1'b1),
+  .fsmcio_rdn(1'b1),
+  .fsmcio_wrn(1'b1),
+  .fsmcio_advn(1'b1)
 );