ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

对FSMC的外部IO仿真接线

Browse Source
This commit is contained in:
Ruige Lee
2025-02-10 11:17:39 +08:00
parent 6ab7cc4590
commit 94acbfae03
4 changed files with 38 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/backBoard/ebus/FSMC2TileLink.scala
View File

@@ -160,12 +160,10 @@ class FSMC2TileLink(implicit p: Parameters) extends LazyModule{
val io = IO(new FSMC_Port_Bundle)
val ( fsmc_bus, fsmc_edge ) = fsmcNode.in.head
// val tla = Wire(new DecoupledIO(new TLBundleA(fsmc_edge.bundle)))
// val tld = Wire(new DecoupledIO(new TLBundleD(fsmc_edge.bundle)))
val sram = Module(new MirrorSRAMDP())
//assert( ~(sram.io.enwA & sram.io.enrA) )
//assert( ~(sram.io.enwB & sram.io.enrB) )
assert( ~(sram.io.enwA & sram.io.enrA) )
assert( ~(sram.io.enwB & sram.io.enrB) )
sram.io.clockA := clock.asBool //system
sram.io.clockB := clock.asBool //system