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对FSMC的外部IO仿真接线

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This commit is contained in:
Ruige Lee
2025-02-10 11:17:39 +08:00
parent 6ab7cc4590
commit 94acbfae03
4 changed files with 38 additions and 33 deletions
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6
src/main/scala/backBoard/ebus/FSMC2TileLink.scala
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@@ -160,12 +160,10 @@ class FSMC2TileLink(implicit p: Parameters) extends LazyModule{
val io = IO(new FSMC_Port_Bundle)
val ( fsmc_bus, fsmc_edge ) = fsmcNode.in.head
// val tla = Wire(new DecoupledIO(new TLBundleA(fsmc_edge.bundle)))
// val tld = Wire(new DecoupledIO(new TLBundleD(fsmc_edge.bundle)))
val sram = Module(new MirrorSRAMDP())
//assert( ~(sram.io.enwA & sram.io.enrA) )
//assert( ~(sram.io.enwB & sram.io.enrB) )
assert( ~(sram.io.enwA & sram.io.enrA) )
assert( ~(sram.io.enwB & sram.io.enrB) )
sram.io.clockA := clock.asBool //system
sram.io.clockB := clock.asBool //system

24
src/main/scala/backBoard/ebus/TL2CDR.scala
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@@ -9,30 +9,6 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
// abstract class BackModule(implicit val p: Parameters) extends Module with HasBackParameters { def io: Record }
// abstract class BackBundle(implicit val p: Parameters) extends Bundle with HasBackParameters
// case object BackParamsKey extends Field[BackSetting]
// case class BackSetting(
// ){
// }
// trait HasBackParameters {
// implicit val p: Parameters
// val backSetting = p(BackParamsKey)
// }
// class BackCfg extends Config((_, _, _) => {
// case BackParamsKey => BackSetting()
// })
class TL2CDR(implicit p: Parameters) extends LazyModule{
val device = new SimpleDevice("TL_CDR", Nil)
val node = TLManagerNode(Seq(TLSlavePortParameters.v1(