ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

aqspi 部分转单线，注意datar_sync和dataw等或许需要增强约束

Browse Source
This commit is contained in:
RuigeLee
2026-01-19 17:28:27 +08:00
parent a78b8edd1a
commit 905c6b96cf
1 changed files with 37 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

58
src/main/scala/backBoard/shin/NSpiInterface.scala
View File

@@ -48,7 +48,9 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
qspi.miso := exRego(7, 4) qspi.miso := exRego(7, 4)
qspi.isDirIn := isSpiWrite | (byteSel <= 3.U) qspi.isDirIn := isSpiWrite | (byteSel <= 3.U)
when( true.B ){ when( byteSel <= 3.U ){ //单线操作
bitSel := bitSel + 1.U
} .otherwise{ //4线操作
bitSel := ~bitSel bitSel := ~bitSel
} }
@@ -56,23 +58,32 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
byteSel := byteSel + 1.U byteSel := byteSel + 1.U
} }
when( bitSel === 0.U ){
exRegi := Cat( 0.U, qspi.mosi ) when( bitSel <= 3.U ){ //单线操作
}.otherwise{ when( bitSel === 0.U ){
exRegi := Cat( exRegi(3,0), qspi.mosi ) exRegi := Cat( 0.U, qspi.mosi.extract(0) )
}.otherwise{
exRegi := Cat( exRegi(6,0), qspi.mosi.extract(0) )
}
} .otherwise{ //4线操作
when( bitSel === 0.U ){
exRegi := Cat( 0.U, qspi.mosi )
}.otherwise{
exRegi := Cat( exRegi(3,0), qspi.mosi )
}
} }
when( bitSel.andR ){
when((byteSel === 1.U || byteSel === 2.U ) ){
exRego := 0.U //地址1，cmd when( bitSel.andR ){ //4线操作
} .elsewhen( isSpiRead ){ when( isSpiRead ){
when( isPing_async ){ //取巧 when( isPing_async ){ //取巧//应该增强约束
exRego := datar_sync(0) exRego := datar_sync(0)
} .otherwise{ } .otherwise{
exRego := datar_sync(1) exRego := datar_sync(1)
} }
} }
} .otherwise{ } .otherwise{ //4线操作
exRego := exRego << 4 exRego := exRego << 4
} }
@@ -83,13 +94,12 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
spiCnt := spiCnt + 1.U spiCnt := spiCnt + 1.U
} }
//单线操作
when( byteSel === 2.U & bitSel.andR ){ when( (byteSel === 2.U & bitSel >= 4.U) || (byteSel === 3.U) ){
spiLenTemp := Cat( qspi.mosi, 0.U(8.W) ) spiLenTemp := Cat( spiLenTemp, qspi.mosi.extract(0) )
} .elsewhen( byteSel === 3.U & bitSel === 0.U ){ }
spiLenTemp := Cat( spiLenTemp(11, 8), qspi.mosi, 0.U(4.W) ) when( byteSel === 3.U & bitSel.andR ){
} .elsewhen( byteSel === 3.U & bitSel.andR ){ spiLen := Cat( spiLenTemp, qspi.mosi.extract(0) )
spiLen := Cat( spiLenTemp(11, 4), qspi.mosi )
} }
@@ -122,8 +132,9 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
} }
} }
//单线操作
when( byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte when( byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
when( qspi.mosi.extract(3) ){ when( qspi.mosi.extract(0) ){
isSpiRead := true.B isSpiRead := true.B
} .otherwise{ } .otherwise{
isSpiWrite := true.B isSpiWrite := true.B
@@ -141,8 +152,8 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
} }
when( when(
(byteSel === 2.U & bitSel === 0.U & (spiCnt <= spiLen) & qspi.mosi === "h8".U) || (byteSel === 2.U & bitSel === 0.U & (spiCnt <= spiLen) & qspi.mosi.extract(0) ) || //单线操作
(byteSel > 2.U & bitSel === 0.U & (spiCnt <= spiLen) & isSpiRead) (byteSel > 2.U & bitSel === 0.U & (spiCnt <= spiLen) & isSpiRead) //混合操作
){ ){
when( ~isPing_async ){ when( ~isPing_async ){
isEnR_async(0) := true.B isEnR_async(0) := true.B
@@ -225,3 +236,8 @@ with SyncSpiSync{
} }
//改spi最大的风险是之前有个负负得正的特性在SM切换上，每次读操作都会多发起一次读才能正确操作SM切换
//速度等级应该可以达到，需要单线转4线
//理论量化分析