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大小端对换，主站已经发出初始化包

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This commit is contained in:
RuigeLee
2024-10-29 18:11:50 +08:00
parent 332fcf010d
commit 9058337ffe
3 changed files with 22 additions and 17 deletions
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26
src/main/scala/backBoard/pico/TLCDR.scala
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@@ -67,10 +67,10 @@ trait TLCDRTx{ this: TLCDRBase =>
txFifo.reset := reset.asBool | isTLWriteTxLen txFifo.reset := reset.asBool | isTLWriteTxLen
CDROut.io.axis.bits.tdata := Mux1H(Seq( CDROut.io.axis.bits.tdata := Mux1H(Seq(
(txCnt === 0.U) -> txData( 7, 0), (txCnt === 0.U) -> txData(31, 24),
(txCnt === 1.U) -> txData(15, 8), (txCnt === 1.U) -> txData(23, 16),
(txCnt === 2.U) -> txData(23, 16), (txCnt === 2.U) -> txData(15, 8),
(txCnt === 3.U) -> txData(31, 24), (txCnt === 3.U) -> txData( 7, 0),
)) ))
CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U
@@ -133,7 +133,7 @@ trait TLCDRRx{ this: TLCDRBase =>
val rxCnt = RegInit(0.U(2.W)) val rxCnt = RegInit(0.U(2.W))
val rxData = Reg(UInt(24.W)) val rxData = Reg(UInt(32.W))
when( isTLWriteRxSoftReset ){ when( isTLWriteRxSoftReset ){
@@ -142,10 +142,10 @@ trait TLCDRRx{ this: TLCDRBase =>
rxCnt := rxCnt + 1.U rxCnt := rxCnt + 1.U
rxData := Mux1H(Seq( rxData := Mux1H(Seq(
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ), (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ), (rxCnt === 1.U) -> Cat( rxData(31,24), CDRIn.io.axis.bits.tdata, 0.U(16.W) ),
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ), (rxCnt === 2.U) -> Cat( rxData(31,16), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ),
// (rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) ), // (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata ),
)) ))
} }
@@ -157,10 +157,10 @@ trait TLCDRRx{ this: TLCDRBase =>
rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.tlast ) rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.tlast )
rxFifo.io.enq.bits := Mux1H(Seq( rxFifo.io.enq.bits := Mux1H(Seq(
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ), (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ), (rxCnt === 1.U) -> Cat( rxData(31,24), CDRIn.io.axis.bits.tdata, 0.U(16.W) ),
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ), (rxCnt === 2.U) -> Cat( rxData(31,16), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ),
(rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) ), (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata ),
)) ))
CDRIn.io.axis.ready := true.B CDRIn.io.axis.ready := true.B

2
tb/backSys_tb.v
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@@ -104,7 +104,7 @@ initial begin
reset <= 0; reset <= 0;
#160000 # 10000000
$display("Time Out !!!"); $display("Time Out !!!");
$stop; $stop;
end end

11
tb/sw/src/mstMain.S
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@@ -20,10 +20,14 @@
main: main:
lui x5, %hi(cdr_0_tx_status) lui x5, %hi(cdr_0_tx_status)
li x6, 128 li x6, 520
sw x6, 4(x5) #cdr_0_tx_txLen sw x6, 4(x5) #cdr_0_tx_txLen
li x6, 32 # 设置循环次数 lui x6, 0x20000
sw x6, 8(x5) # 发送len op param0
sw x0, 8(x5) # 发送 param1 param2
li x6, 128 # 设置循环次数
li x10, 0x1234
1: 1:
beqz x15, 3f # 如果x10为0，则跳到3 beqz x15, 3f # 如果x10为0，则跳到3
2: 2:
@@ -34,7 +38,8 @@ main:
3: 3:
# 向cdr_0_tx_txFifo地址写入0x55，循环32次 # 向cdr_0_tx_txFifo地址写入0x55，循环32次
sw x6, 8(x5) # 向cdr_0_tx_txFifo写入0x55
sw x10, 8(x5) # 向cdr_0_tx_txFifo写入0
addi x6, x6, -1 # 递减计数器 addi x6, x6, -1 # 递减计数器
bnez x6, 1b # 如果计数器不为0，则继续循环 bnez x6, 1b # 如果计数器不为0，则继续循环