diff --git a/src/main/scala/backBoard/pico/TLCDR.scala b/src/main/scala/backBoard/pico/TLCDR.scala
index cf8a2fd..757a7ae 100644
--- a/src/main/scala/backBoard/pico/TLCDR.scala
+++ b/src/main/scala/backBoard/pico/TLCDR.scala
@@ -67,10 +67,10 @@ trait TLCDRTx{ this: TLCDRBase =>
   txFifo.reset := reset.asBool | isTLWriteTxLen
 
   CDROut.io.axis.bits.tdata := Mux1H(Seq(
-    (txCnt === 0.U) -> txData( 7,  0),
-    (txCnt === 1.U) -> txData(15,  8),
-    (txCnt === 2.U) -> txData(23, 16),
-    (txCnt === 3.U) -> txData(31, 24),
+    (txCnt === 0.U) -> txData(31, 24),
+    (txCnt === 1.U) -> txData(23, 16),
+    (txCnt === 2.U) -> txData(15,  8),
+    (txCnt === 3.U) -> txData( 7,  0),
   ))
 
   CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U
@@ -133,7 +133,7 @@ trait TLCDRRx{ this: TLCDRBase =>
 
 
   val rxCnt = RegInit(0.U(2.W))
-  val rxData = Reg(UInt(24.W))
+  val rxData = Reg(UInt(32.W))
 
   
   when( isTLWriteRxSoftReset ){
@@ -142,10 +142,10 @@ trait TLCDRRx{ this: TLCDRBase =>
     rxCnt :=  rxCnt + 1.U
 
     rxData := Mux1H(Seq(
-      (rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ),
-      (rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ),
-      (rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ),
-      // (rxCnt === 3.U) -> Cat(                CDRIn.io.axis.bits.tdata, rxData(23,0) ),
+      (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
+      (rxCnt === 1.U) -> Cat( rxData(31,24), CDRIn.io.axis.bits.tdata, 0.U(16.W) ),
+      (rxCnt === 2.U) -> Cat( rxData(31,16), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ),
+      // (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata  ),
     ))
   }
 
@@ -157,10 +157,10 @@ trait TLCDRRx{ this: TLCDRBase =>
 
   rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.tlast )
   rxFifo.io.enq.bits  := Mux1H(Seq(
-      (rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ),
-      (rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ),
-      (rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ),
-      (rxCnt === 3.U) -> Cat(            CDRIn.io.axis.bits.tdata, rxData(23,0) ),
+      (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
+      (rxCnt === 1.U) -> Cat( rxData(31,24), CDRIn.io.axis.bits.tdata, 0.U(16.W) ),
+      (rxCnt === 2.U) -> Cat( rxData(31,16), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ),
+      (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata  ),
     ))
   CDRIn.io.axis.ready := true.B
 
diff --git a/tb/backSys_tb.v b/tb/backSys_tb.v
index 7151b72..53101b8 100644
--- a/tb/backSys_tb.v
+++ b/tb/backSys_tb.v
@@ -104,7 +104,7 @@ initial begin
 
 	reset <= 0;
 
-	#160000
+	# 10000000
 			$display("Time Out !!!");
 	$stop;
 end
diff --git a/tb/sw/src/mstMain.S b/tb/sw/src/mstMain.S
index acc1343..512596c 100644
--- a/tb/sw/src/mstMain.S
+++ b/tb/sw/src/mstMain.S
@@ -20,10 +20,14 @@
 main:
 	lui  x5, %hi(cdr_0_tx_status)
 
-	li   x6, 128
+	li   x6, 520
 	sw	 x6, 4(x5) #cdr_0_tx_txLen
 
-    li   x6, 32              # 设置循环次数
+    lui x6, 0x20000
+    sw   x6, 8(x5)           # 发送len op param0
+    sw   x0, 8(x5)           # 发送 param1 param2
+    li   x6, 128              # 设置循环次数
+    li x10, 0x1234
 1:
 	beqz x15, 3f             # 如果x10为0，则跳到3
 2:
@@ -34,7 +38,8 @@ main:
 
 3:
     # 向cdr_0_tx_txFifo地址写入0x55，循环32次
-    sw   x6, 8(x5)          # 向cdr_0_tx_txFifo写入0x55
+
+    sw   x10, 8(x5)          # 向cdr_0_tx_txFifo写入0
     addi x6, x6, -1         # 递减计数器
     bnez x6, 1b             # 如果计数器不为0，则继续循环