ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

大小端对换，主站已经发出初始化包

Browse Source
This commit is contained in:
RuigeLee
2024-10-29 18:11:50 +08:00
parent 332fcf010d
commit 9058337ffe
3 changed files with 22 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
src/main/scala/backBoard/pico/TLCDR.scala
View File

@@ -67,10 +67,10 @@ trait TLCDRTx{ this: TLCDRBase =>
txFifo.reset := reset.asBool | isTLWriteTxLen
CDROut.io.axis.bits.tdata := Mux1H(Seq(
(txCnt === 0.U) -> txData( 7, 0),
(txCnt === 1.U) -> txData(15, 8),
(txCnt === 2.U) -> txData(23, 16),
(txCnt === 3.U) -> txData(31, 24),
(txCnt === 0.U) -> txData(31, 24),
(txCnt === 1.U) -> txData(23, 16),
(txCnt === 2.U) -> txData(15, 8),
(txCnt === 3.U) -> txData( 7, 0),
))
CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U
@@ -133,7 +133,7 @@ trait TLCDRRx{ this: TLCDRBase =>
val rxCnt = RegInit(0.U(2.W))
val rxData = Reg(UInt(24.W))
val rxData = Reg(UInt(32.W))
when( isTLWriteRxSoftReset ){
@@ -142,10 +142,10 @@ trait TLCDRRx{ this: TLCDRBase =>
rxCnt := rxCnt + 1.U
rxData := Mux1H(Seq(
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ),
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ),
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ),
// (rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) ),
(rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
(rxCnt === 1.U) -> Cat( rxData(31,24), CDRIn.io.axis.bits.tdata, 0.U(16.W) ),
(rxCnt === 2.U) -> Cat( rxData(31,16), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ),
// (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata ),
))
}
@@ -157,10 +157,10 @@ trait TLCDRRx{ this: TLCDRBase =>
rxFifo.io.enq.valid := CDRIn.io.axis.fire & ( rxCnt === 3.U | CDRIn.io.axis.bits.tlast )
rxFifo.io.enq.bits := Mux1H(Seq(
(rxCnt === 0.U) -> Cat( 0.U(24.W), CDRIn.io.axis.bits.tdata ),
(rxCnt === 1.U) -> Cat( 0.U(16.W), CDRIn.io.axis.bits.tdata, rxData( 7,0) ),
(rxCnt === 2.U) -> Cat( 0.U(8.W ), CDRIn.io.axis.bits.tdata, rxData(15,0) ),
(rxCnt === 3.U) -> Cat( CDRIn.io.axis.bits.tdata, rxData(23,0) ),
(rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
(rxCnt === 1.U) -> Cat( rxData(31,24), CDRIn.io.axis.bits.tdata, 0.U(16.W) ),
(rxCnt === 2.U) -> Cat( rxData(31,16), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ),
(rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata ),
))
CDRIn.io.axis.ready := true.B