remove rxabort again

src/main/scala/Switch/MacRegisters.scala

@@ -29,7 +29,6 @@ class Mac_Config_Bundle extends Bundle{
   val RxClk               = Input(Bool())
   val SetPauseTimer       = Input(Bool())
 
-  val r_RecSmall  = Output(Bool())
   val r_Pad       = Output(Bool())
   val r_HugEn     = Output(Bool())
   val r_CrcEn     = Output(Bool())
@@ -39,9 +38,7 @@ class Mac_Config_Bundle extends Bundle{
   val r_NoBckof   = Output(Bool())
   val r_LoopBck   = Output(Bool())
   val r_IFG       = Output(Bool())
-  val r_Pro       = Output(Bool())
   val r_Iam       = Output(Bool())
-  val r_Bro       = Output(Bool())
   val r_NoPre     = Output(Bool())
   val r_TxEn      = Output(Bool())
   val r_RxEn      = Output(Bool())
@@ -56,7 +53,6 @@ class Mac_Config_Bundle extends Bundle{
   val r_CollValid = Output(UInt(6.W))
   val r_TxFlow    = Output(Bool())
   val r_RxFlow    = Output(Bool())
-  val r_PassAll   = Output(Bool())
   val r_MiiNoPre  = Output(Bool())
   val r_ClkDiv    = Output(UInt(8.W))
   val r_WCtrlData = Output(Bool())
@@ -111,7 +107,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
     val (int, _) = outer.int_node.out(0)
 
 
-    val RecSmall  = RegInit(false.B)
     val Pad       = RegInit(true.B)
     val HugEn     = RegInit(false.B)
     val CrcEn     = RegInit(true.B)
@@ -122,9 +117,7 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
     val NoBckof   = RegInit(false.B)
     val LoopBck   = RegInit(false.B)
     val IFG       = RegInit(false.B)
-    val Pro       = RegInit(false.B)
     val Iam       = RegInit(false.B)
-    val Bro       = RegInit(false.B)
     val NoPre     = RegInit(false.B)
     val TxEn      = RegInit(false.B)
     val RxEn      = RegInit(false.B)
@@ -157,7 +150,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
 
     val txFlow  = RegInit(false.B)
     val rxFlow  = RegInit(false.B)
-    val passAll = RegInit(false.B)
 
     val clkDiv = RegInit("h64".U(8.W))
     val miiNoPre = RegInit(false.B)
@@ -207,9 +199,9 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
           RegField(1, RxEn   , RegFieldDesc( "RxEn", "RxEn", reset = Some(0))) ,
           RegField(1, TxEn   , RegFieldDesc( "TxEn", "TxEn", reset = Some(0) ) ),
           RegField(1, NoPre  , RegFieldDesc( "NoPre", "NoPre", reset = Some(0) ) ),
-          RegField(1, Bro    , RegFieldDesc( "Bro", "Bro", reset = Some(0) ) ),
+          RegField.r(1, 0.U  , RegFieldDesc( "Bro", "Bro", reset = Some(0) ) ),
           RegField(1, Iam    , RegFieldDesc( "Iam", "Iam", reset = Some(0) ) ),
-          RegField(1, Pro    , RegFieldDesc( "Pro", "Pro", reset = Some(0) ) ),
+          RegField.r(1, 0.U  , RegFieldDesc( "Pro", "Pro", reset = Some(0) ) ),
           RegField(1, IFG    , RegFieldDesc( "IFG", "IFG", reset = Some(0) ) ),
           RegField(1, LoopBck, RegFieldDesc( "LoopBck", "LoopBck", reset = Some(0) ) ),
           RegField(1, NoBckof, RegFieldDesc( "NoBckof", "NoBckof", reset = Some(0) ) ),
@@ -220,7 +212,7 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
           RegField(1, CrcEn   , RegFieldDesc( "CrcEn", "CrcEn",       reset=Some(1)) ),
           RegField(1, HugEn   , RegFieldDesc( "HugEn", "HugEn",       reset=Some(0)) ),
           RegField(1, Pad     , RegFieldDesc( "Pad", "Pad",           reset=Some(1)) ),
-          RegField(1, RecSmall, RegFieldDesc( "RecSmall", "RecSmall", reset=Some(0)) )
+          RegField.r(1, 1.U,    RegFieldDesc( "RecSmall", "RecSmall", reset=Some(0)) )
         )),
 
       ( 1 << 2 ) ->
@@ -272,7 +264,7 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
 
       ( 9 << 2 ) ->
         RegFieldGroup("CTRLMODER", Some("Control Module Mode Register"), Seq(
-          RegField(1, passAll, RegFieldDesc("PassAll", "Pass All Receive Frames", reset=Some(0))),
+          RegField.r(1, 1.U, RegFieldDesc("PassAll", "Pass All Receive Frames", reset=Some(0))),
           RegField(1, rxFlow , RegFieldDesc("RxFlow", "Receive Flow Control", reset=Some(0))),
           RegField(1, txFlow , RegFieldDesc("TxFlow", "Transmit Flow Control", reset=Some(0))),
         )),
@@ -366,7 +358,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
 
 
 
-    io.r_RecSmall  := RecSmall
     io.r_Pad       := Pad
     io.r_HugEn     := HugEn
     io.r_CrcEn     := CrcEn
@@ -376,9 +367,7 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
     io.r_NoBckof   := NoBckof
     io.r_LoopBck   := LoopBck
     io.r_IFG       := IFG
-    io.r_Pro       := Pro
     io.r_Iam       := Iam
-    io.r_Bro       := Bro
     io.r_NoPre     := NoPre
     io.r_TxEn     := TxEn & (TX_BD_NUM > 0.U)      // Transmission is enabled when there is at least one TxBD.
     io.r_RxEn     := RxEn & (TX_BD_NUM < "h80".U)  // Reception is enabled when there is  at least one RxBD.
@@ -392,7 +381,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
     io.r_CollValid := collValid
     io.r_TxFlow    := txFlow
     io.r_RxFlow    := rxFlow
-    io.r_PassAll   := passAll
     io.r_MiiNoPre  := miiNoPre
     io.r_ClkDiv    := clkDiv
     io.r_WCtrlData := wCtrlData

src/main/scala/Switch/RxBuff.scala

@@ -6,7 +6,6 @@ import chisel3.util._
 class Receive_Enq_Ctrl_Bundle extends Bundle{
   val LatchedRxLength   = UInt(16.W)
   val RxStatusInLatched = UInt(9.W)
-  val isRxAbort         = Bool()
 }
 
 class Receive_Deq_Ctrl_Bundle extends Receive_Enq_Ctrl_Bundle{
@@ -76,10 +75,7 @@ trait RxBuffEnq{ this: RxBuffBase =>
   io.enq.data.ready := (isEnqPi & buff(0).io.enq.ready) | (isEnqPo & buff(1).io.enq.ready)
   io.enq.ctrl.ready := true.B
 
-  buff(0).reset := reset.asBool | (isEnqPi & io.enq.ctrl.fire & io.enq.ctrl.bits.isRxAbort)
+  when( io.enq.ctrl.fire ){
-  buff(1).reset := reset.asBool | (isEnqPo & io.enq.ctrl.fire & io.enq.ctrl.bits.isRxAbort)
-
-  when( io.enq.ctrl.fire & ~io.enq.ctrl.bits.isRxAbort){
     isEnqPi := ~isEnqPi
     when( isEnqPi ){
       info(0)   := io.enq.ctrl.bits

src/main/scala/Switch/mac/MAC.scala

@@ -139,9 +139,6 @@ val miim = Module(new MIIM)
 
 
 
-
-
-val r_RecSmall                 = Wire(Bool())
 val r_LoopBck                  = Wire(Bool())
 val r_TxEn                     = Wire(Bool())
 val r_RxEn                     = Wire(Bool())
@@ -153,7 +150,6 @@ val r_HugEn                    = Wire(Bool())
 val r_DlyCrcEn                 = Wire(Bool())
 val r_MaxFL                    = Wire(UInt(16.W))
 val r_MinFL                    = Wire(UInt(16.W))
-val ShortFrame                 = Wire(Bool())
 val DribbleNibble              = Wire(Bool())
 val ReceivedPacketTooBig       = Wire(Bool())
 val r_MAC                      = Wire(UInt(48.W))
@@ -180,11 +176,8 @@ val Busy_IRQ                   = Wire(Bool())
 val r_Pad                      = Wire(Bool())
 val r_CrcEn                    = Wire(Bool())
 val r_FullD                    = Wire(Bool())
-val r_Pro                      = Wire(Bool())
-val r_Bro                      = Wire(Bool())
 val r_NoPre                    = Wire(Bool())
 val r_RxFlow                   = Wire(Bool())
-val r_PassAll                  = Wire(Bool())
 val TxCtrlEndFrm               = Wire(Bool())
 val StartTxDone                = Wire(Bool())
 val SetPauseTimer              = Wire(Bool())
@@ -207,7 +200,6 @@ val DeferLatched               = Wire(Bool())
 val RstDeferLatched            = Wire(Bool())
 val CarrierSenseLost           = Wire(Bool())
 
-dontTouch(r_RecSmall                 )
 dontTouch(r_LoopBck                  )
 dontTouch(r_TxEn                     )
 dontTouch(r_RxEn                     )
@@ -219,7 +211,6 @@ dontTouch(r_HugEn                    )
 dontTouch(r_DlyCrcEn                 )
 dontTouch(r_MaxFL                    )
 dontTouch(r_MinFL                    )
-dontTouch(ShortFrame                 )
 dontTouch(DribbleNibble              )
 dontTouch(ReceivedPacketTooBig       )
 dontTouch(r_MAC                      )
@@ -246,11 +237,8 @@ dontTouch(Busy_IRQ                   )
 dontTouch(r_Pad                      )
 dontTouch(r_CrcEn                    )
 dontTouch(r_FullD                    )
-dontTouch(r_Pro                      )
-dontTouch(r_Bro                      )
 dontTouch(r_NoPre                    )
 dontTouch(r_RxFlow                   )
-dontTouch(r_PassAll                  )
 dontTouch(TxCtrlEndFrm               )
 dontTouch(StartTxDone                )
 dontTouch(SetPauseTimer              )
@@ -300,8 +288,6 @@ io.cfg.TxClk               := io.mii.mtx_clk_pad_i
 io.cfg.RxClk               := io.mii.mrx_clk_pad_i
 io.cfg.SetPauseTimer       := SetPauseTimer
 
-
-r_RecSmall  := io.cfg.r_RecSmall
 r_Pad       := io.cfg.r_Pad
 r_HugEn     := io.cfg.r_HugEn
 r_CrcEn     := io.cfg.r_CrcEn
@@ -311,8 +297,6 @@ r_ExDfrEn   := io.cfg.r_ExDfrEn
 r_NoBckof   := io.cfg.r_NoBckof
 r_LoopBck   := io.cfg.r_LoopBck
 r_IFG       := io.cfg.r_IFG
-r_Pro       := io.cfg.r_Pro
-r_Bro       := io.cfg.r_Bro
 r_NoPre     := io.cfg.r_NoPre
 r_TxEn      := io.cfg.r_TxEn
 r_RxEn      := io.cfg.r_RxEn
@@ -327,7 +311,6 @@ r_MaxRet    := io.cfg.r_MaxRet
 r_CollValid := io.cfg.r_CollValid
 r_TxFlow    := io.cfg.r_TxFlow
 r_RxFlow    := io.cfg.r_RxFlow
-r_PassAll   := io.cfg.r_PassAll
 r_MiiNoPre  := io.cfg.r_MiiNoPre
 r_ClkDiv    := io.cfg.r_ClkDiv
 r_WCtrlData := io.cfg.r_WCtrlData
@@ -348,7 +331,6 @@ val RxData               = Wire(UInt(8.W))
 val RxValid              = Wire(Bool())
 val RxStartFrm           = Wire(Bool())
 val RxEndFrm             = Wire(Bool())
-val RxAbort              = Wire(Bool())
 val WillTransmit         = Wire(Bool())
 val ResetCollision       = Wire(Bool())
 val TxDataOut            = Wire(UInt(8.W))
@@ -356,7 +338,6 @@ val WillSendControlFrame = Wire(Bool())
 val ReceiveEnd           = Wire(Bool())
 val ReceivedPacketGood   = Wire(Bool())
 val ReceivedLengthOK     = Wire(Bool())
-val InvalidSymbol        = Wire(Bool())
 val LatchedCrcError      = Wire(Bool())
 val RxLateCollision      = Wire(Bool())
 val RetryCntLatched      = Wire(UInt(4.W))  
@@ -371,7 +352,6 @@ dontTouch(RxData              )
 dontTouch(RxValid             )
 dontTouch(RxStartFrm          )
 dontTouch(RxEndFrm            )
-dontTouch(RxAbort             )
 dontTouch(WillTransmit        )
 dontTouch(ResetCollision      )
 dontTouch(TxDataOut           )
@@ -379,7 +359,6 @@ dontTouch(WillSendControlFrame)
 dontTouch(ReceiveEnd          )
 dontTouch(ReceivedPacketGood  )
 dontTouch(ReceivedLengthOK    )
-dontTouch(InvalidSymbol       )
 dontTouch(LatchedCrcError     )
 dontTouch(RxLateCollision     )
 dontTouch(RetryCntLatched     )
@@ -420,7 +399,6 @@ maccontrol.io.DlyCrcEn                   := r_DlyCrcEn
 maccontrol.io.TxPauseTV                  := r_TxPauseTV
 maccontrol.io.MAC                        := r_MAC
 maccontrol.io.RxStatusWriteLatched_sync2 := RxStatusWriteLatchedSync
-maccontrol.io.r_PassAll                  := r_PassAll
 
 TxDataOut := maccontrol.io.TxDataOut
 TxStartFrmOut := maccontrol.io.TxStartFrmOut
@@ -541,11 +519,9 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   rxethmac.io.MaxFL               := r_MaxFL
   rxethmac.io.r_IFG               := r_IFG
   rxethmac.io.MAC                 := r_MAC
-  rxethmac.io.r_Bro               := r_Bro
-  rxethmac.io.r_Pro               := r_Pro
   rxethmac.io.r_HASH0             := r_HASH0
   rxethmac.io.r_HASH1             := r_HASH1
-  rxethmac.io.PassAll             := r_PassAll
+  rxethmac.io.PassAll             := true.B
   rxethmac.io.ControlFrmAddressOK := ControlFrmAddressOK
 
   RxData            := rxethmac.io.RxData
@@ -561,7 +537,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   RxStatePreamble   := rxethmac.io.StatePreamble
   RxStateSFD        := rxethmac.io.StateSFD
   RxStateData       := rxethmac.io.StateData
-  RxAbort           := rxethmac.io.RxAbort
   AddressMiss       := rxethmac.io.AddressMiss
 
 
@@ -613,29 +588,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
     TPauseRq := RegNext( TxPauseRq_sync(1) & (~TxPauseRq_sync(2)), false.B )
   }
 
-  val LatchedMRxErr = Wire(Bool())
-
-
-
-
-  val RxAbort_latch_wire = Wire(Bool())
-  val RxAbort_wb = ShiftRegister( RxAbort_latch_wire, 2, false.B, true.B )
-
-  withClockAndReset( io.mii.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
-    val RxAbort_latch = RegInit(false.B); RxAbort_latch_wire := RxAbort_latch
-    val RxAbortRst = ShiftRegister( RxAbort_wb, 2, false.B, true.B )
-    
-    // Synchronizing RxAbort to the WISHBONE clock
-    when(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll))){
-      RxAbort_latch := true.B
-    } .elsewhen(RxAbortRst){
-      RxAbort_latch := false.B
-    }
-
-  }
-
-
-
 
   val wishbone = Module(new MacTileLink)
 
@@ -678,7 +630,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   macstatus.io.MRxD                := MRxD_Lb
   macstatus.io.Collision           := io.mii.mcoll_pad_i
   macstatus.io.CollValid           := r_CollValid
-  macstatus.io.r_RecSmall          := r_RecSmall
   macstatus.io.r_MinFL             := r_MinFL
   macstatus.io.r_MaxFL             := r_MaxFL
   macstatus.io.r_HugEn             := r_HugEn
@@ -700,10 +651,8 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   ReceivedLengthOK     := macstatus.io.ReceivedLengthOK
   ReceiveEnd           := macstatus.io.ReceiveEnd
   ReceivedPacketGood   := macstatus.io.ReceivedPacketGood
-  InvalidSymbol        := macstatus.io.InvalidSymbol
   LatchedCrcError      := macstatus.io.LatchedCrcError
   RxLateCollision      := macstatus.io.RxLateCollision
-  ShortFrame           := macstatus.io.ShortFrame
   DribbleNibble        := macstatus.io.DribbleNibble
   ReceivedPacketTooBig := macstatus.io.ReceivedPacketTooBig
   LoadRxStatus         := macstatus.io.LoadRxStatus
@@ -712,7 +661,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   LateCollLatched      := macstatus.io.LateCollLatched
   DeferLatched         := macstatus.io.DeferLatched
   CarrierSenseLost     := macstatus.io.CarrierSenseLost
-  LatchedMRxErr        := macstatus.io.LatchedMRxErr
 
 
 
@@ -743,9 +691,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   }
 
 
-
-
-
   withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ){
     macTileLinkTx.io.BlockingTxStatusWrite_sync := ShiftRegister( wishbone.io.BlockingTxStatusWrite, 2, false.B, true.B)
   }
@@ -756,9 +701,8 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   TxEndFrm        := macTileLinkTx.io.TxEndFrm
   TxData          := macTileLinkTx.io.TxData
 
-  // macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb
   
-              wishbone.io.TxUsedData      := TxUsedData
+  wishbone.io.TxUsedData      := TxUsedData
   macTileLinkTx.io.TxUsedData := TxUsedData
 
   macTileLinkTx.io.TxRetry    := TxRetry
@@ -791,15 +735,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
 
 
   val macTileLinkRx = withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRx) )
-
+ 
-
-
-
-
-
-  val RxAbortSync           = ShiftRegister( macTileLinkRx.io.RxAbortLatched, 2, false.B, true.B )
-  wishbone.io.RxAbortSync  := RxAbortSync
-  
 
   val req_ToAsync = Wire(new AsyncBundle(new RxFifo_Stream_Bundle))
   val resp_ToAsync = Wire(new AsyncBundle(Bool()))
@@ -831,14 +767,12 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
 
   withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) {
     RxStatusWriteLatchedSync         := fateRxRespPort.fire
-    macTileLinkRx.io.RxAbortSyncb    := ShiftRegister( RxAbortSync,    2, false.B, true.B )
     macTileLinkRx.io.Busy_IRQ_syncb  := ShiftRegister( Busy_IRQ_sync,  2, false.B, true.B )
 
     macTileLinkRx.io.RxReady  := ShiftRegister( wishbone.io.RxReady, 2, false.B, true.B )
   }
 
   macTileLinkRx.io.RxData   := RxData
-  macTileLinkRx.io.RxAbort  := RxAbort_latch_wire
   macTileLinkRx.io.RxValid  := RxValid
 
   macTileLinkRx.io.RxStartFrm := RxStartFrm
@@ -847,7 +781,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
 
   macTileLinkRx.io.RxLength     := RxByteCnt
   macTileLinkRx.io.LoadRxStatus := LoadRxStatus
-  macTileLinkRx.io.RxStatusIn   := Cat(ReceivedPauseFrm, AddressMiss, false.B, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision)
+  macTileLinkRx.io.RxStatusIn   := Cat(ReceivedPauseFrm, AddressMiss, false.B, false.B, DribbleNibble, ReceivedPacketTooBig, false.B, LatchedCrcError, RxLateCollision)
 
 
   wishbone.io.rxEnq <> io.rxEnq

src/main/scala/Switch/mac/MacControl.scala

@@ -31,7 +31,6 @@ val DlyCrcEn                   = Input(Bool())             // Delayed CRC enable
 val TxPauseTV                  = Input(UInt(16.W))         // Transmit Pause Timer Value (from registers)
 val MAC                        = Input(UInt(48.W))         // MAC address (from registers)
 val RxStatusWriteLatched_sync2 = Input(Bool())
-val r_PassAll                  = Input(Bool())
 
 val TxDataOut                  = Output(UInt(8.W))         // Transmit Packet Data (to TxEthMAC)
 val TxStartFrmOut              = Output(Bool())            // Transmit packet start frame (output to TxEthMAC)
@@ -420,7 +419,7 @@ class MacControl extends RawModule{
 
     val ReceivedPauseFrm = RegInit(false.B); io.ReceivedPauseFrm := ReceivedPauseFrm // Pause Frame received
 
-    when((io.RxStatusWriteLatched_sync2 & io.r_PassAll) | (ReceivedPauseFrm & (~io.r_PassAll))){
+    when(io.RxStatusWriteLatched_sync2 ){
       ReceivedPauseFrm := false.B
     } .elsewhen(ByteCntEq16 & TypeLengthOK & OpCodeOK){
       ReceivedPauseFrm := true.B

src/main/scala/Switch/mac/MacRx.scala

@@ -15,8 +15,6 @@ class MacRxIO extends Bundle{
   val MaxFL               = Input(UInt(16.W))
   val r_IFG               = Input(Bool())
   val MAC                 = Input(UInt(48.W))     //  Station Address  
-  val r_Bro               = Input(Bool())       //  broadcast disable
-  val r_Pro               = Input(Bool())       //  promiscuous enable 
   val r_HASH0             = Input(UInt(32.W)) //  lower 4 bytes Hash Table
   val r_HASH1             = Input(UInt(32.W)) //  upper 4 bytes Hash Table
   val PassAll             = Input(Bool())
@@ -35,7 +33,6 @@ class MacRxIO extends Bundle{
   val StatePreamble   = Output(Bool())
   val StateSFD        = Output(Bool())
   val StateData       = Output(UInt(2.W))
-  val RxAbort         = Output(Bool())
   val AddressMiss     = Output(Bool())
 }
 
@@ -73,9 +70,6 @@ abstract class MacRxBase extends Module with RequireAsyncReset{
   val RxData_d = RegInit(0.U(8.W))
   val RxData = RegNext(RxData_d, 0.U); io.RxData := RxData
 
-  val Broadcast = RegInit(false.B)
-  val Multicast = RegInit(false.B)
-
   val Crc = RegInit("hFFFFFFFF".U(32.W))
 
 
@@ -202,58 +196,23 @@ trait MacRxFAddrCheck { this: MacRxBase =>
 
   val HashBit = Wire(UInt(1.W))
 
-
-  val BroadcastOK = Broadcast & ~io.r_Bro
   val RxCheckEn   = io.StateData.orR
 
-  val RxAbort = RegInit(false.B)  // Address Error Reported at end of address cycle// RxAbort clears after one cycle
   val AddressMiss = RegInit(false.B) // This ff holds the "Address Miss" information that is written to the RX BD status. 
-  val MulticastOK = RegInit(false.B) // Hash Address Check, Multicast
-  val UnicastOK = RegInit(false.B)  // Address Detection (unicast)  // start with ByteCntEq2 due to delay of addres from RxData
 
-  io.RxAbort     := RxAbort
   io.AddressMiss := AddressMiss
 
 
-  val RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | io.r_Pro);
+
 
   val CrcHash = RegInit(0.U(6.W))
   val CrcHashGood = RegNext(StateData0 & ByteCntEq6) // Latching CRC for use in the hash table
 
-  when(RxAddressInvalid & ByteCntEq7 & RxCheckEn){
-    RxAbort := true.B  
-  } .otherwise{
-    RxAbort := false.B
-  }
-
   when(ByteCntEq0){
     AddressMiss := false.B
   } .elsewhen(ByteCntEq7 & RxCheckEn){
-    AddressMiss := (~(UnicastOK | BroadcastOK | MulticastOK | (io.PassAll & io.ControlFrmAddressOK)));    
+    AddressMiss := (~((io.PassAll & io.ControlFrmAddressOK)));    
   }
-
-  when(io.RxEndFrm | RxAbort){
-    MulticastOK := false.B
-  } .elsewhen(CrcHashGood & Multicast){
-    MulticastOK := HashBit
-  }
-
-  when(RxCheckEn & ByteCntEq2){
-    UnicastOK := RxData === io.MAC(47,40)
-  } .elsewhen(RxCheckEn & ByteCntEq3){
-    UnicastOK := ( RxData === io.MAC(39,32)) & UnicastOK
-  } .elsewhen(RxCheckEn & ByteCntEq4){
-    UnicastOK := ( RxData === io.MAC(31,24)) & UnicastOK
-  } .elsewhen(RxCheckEn & ByteCntEq5){
-    UnicastOK := ( RxData === io.MAC(23,16)) & UnicastOK
-  } .elsewhen(RxCheckEn & ByteCntEq6){
-    UnicastOK := ( RxData === io.MAC(15,8))  & UnicastOK
-  } .elsewhen(RxCheckEn & ByteCntEq7){
-    UnicastOK := ( RxData === io.MAC(7,0))   & UnicastOK
-  } .elsewhen(io.RxEndFrm | RxAbort){
-    UnicastOK := false.B
-  }
-
    
   val IntHash = Mux(CrcHash.extract(5), io.r_HASH1, io.r_HASH0)
   val ByteHash = 
@@ -344,23 +303,6 @@ class MacRx extends MacRxBase with MacRxFSM with MacRxCounter with MacRxFAddrChe
     RxData_d := 0.U        // Delaying data to be valid for two cycles.        // Zero when not active.
   }
 
- 
-  when(StateData0 & LatchedByte =/= "hFF".U & ByteCntSmall7){
-    Broadcast := false.B
-  } .elsewhen(StateData0 & LatchedByte === "hFF".U & ByteCntEq1){
-    Broadcast := true.B
-  } .elsewhen(io.RxAbort | io.RxEndFrm){
-    Broadcast := false.B
-  }
-
-     
-  when(StateData0 & ByteCntEq1 & LatchedByte.extract(0)){
-    Multicast := true.B
-  } .elsewhen(io.RxAbort | io.RxEndFrm){
-    Multicast := false.B
-  }
-
-
 
   io.RxValid := ShiftRegister(GenerateRxValid, 2, false.B, true.B)
 

src/main/scala/Switch/mac/MacStatus.scala

@@ -22,7 +22,6 @@ class MacStatusIO extends Bundle{
   val MRxD                = Input(UInt(4.W))
   val Collision           = Input(Bool())
   val CollValid           = Input(UInt(6.W))
-  val r_RecSmall          = Input(Bool())
   val r_MinFL             = Input(UInt(16.W))
   val r_MaxFL             = Input(UInt(16.W))
   val r_HugEn             = Input(Bool())
@@ -44,10 +43,8 @@ class MacStatusIO extends Bundle{
   val ReceivedLengthOK     = Output(Bool())
   val ReceiveEnd           = Output(Bool())
   val ReceivedPacketGood   = Output(Bool())
-  val InvalidSymbol        = Output(Bool())
   val LatchedCrcError      = Output(Bool())
   val RxLateCollision      = Output(Bool())
-  val ShortFrame           = Output(Bool())
   val DribbleNibble        = Output(Bool())
   val ReceivedPacketTooBig = Output(Bool())
   val LoadRxStatus         = Output(Bool())
@@ -56,7 +53,6 @@ class MacStatusIO extends Bundle{
   val LateCollLatched      = Output(Bool())
   val DeferLatched         = Output(Bool())
   val CarrierSenseLost     = Output(Bool())
-  val LatchedMRxErr        = Output(Bool())
 }
 
 class MacStatus extends RawModule{
@@ -73,13 +69,6 @@ class MacStatus extends RawModule{
     }
 
 
-    val LatchedMRxErr = RegInit(false.B); io.LatchedMRxErr := LatchedMRxErr // LatchedMRxErr
-
-    when(io.MRxErr & io.MRxDV & (io.RxStatePreamble | io.RxStateSFD | io.RxStateData.orR | io.RxStateIdle & ~io.Transmitting)){
-      LatchedMRxErr := true.B
-    } .otherwise{
-      LatchedMRxErr := false.B
-    }
 
     io.ReceivedPacketGood := ~LatchedCrcError                                        // ReceivedPacketGood
     io.ReceivedLengthOK := io.RxByteCnt >= io.r_MinFL & io.RxByteCnt <= io.r_MaxFL   // ReceivedLengthOK
@@ -92,14 +81,8 @@ class MacStatus extends RawModule{
     
     val LoadRxStatus = RegNext(TakeSample, false.B); io.LoadRxStatus := LoadRxStatus // LoadRxStatus
     val ReceiveEnd = RegNext(LoadRxStatus, false.B); io.ReceiveEnd := ReceiveEnd     // ReceiveEnd
-    val SetInvalidSymbol = io.MRxDV & io.MRxErr & io.MRxD === "he".U                 // Invalid symbol was received during reception in 100Mbps 
-    val InvalidSymbol = RegInit(false.B); io.InvalidSymbol := InvalidSymbol          // InvalidSymbol
 
-    when(LoadRxStatus & ~SetInvalidSymbol){
+
-      InvalidSymbol := false.B
-    } .elsewhen(SetInvalidSymbol){
-      InvalidSymbol := true.B
-    }
 
 
     val RxLateCollision = RegInit(false.B); io.RxLateCollision := RxLateCollision // Late Collision
@@ -107,7 +90,7 @@ class MacStatus extends RawModule{
 
     when(LoadRxStatus){
       RxLateCollision := false.B
-    } .elsewhen(io.Collision & (~io.r_FullD) & (~RxColWindow | io.r_RecSmall)){
+    } .elsewhen(io.Collision & (~io.r_FullD) ){
       RxLateCollision := true.B
     }
 
@@ -117,12 +100,7 @@ class MacStatus extends RawModule{
       RxColWindow := true.B
     }
 
-    val ShortFrame = RegInit(false.B); io.ShortFrame := ShortFrame //ShortFrame
+
-    when(LoadRxStatus){
-      ShortFrame := false.B
-    } .elsewhen(TakeSample){
-      ShortFrame := io.RxByteCnt < io.r_MinFL    
-    }
 
 
     // DribbleNibble

src/main/scala/Switch/mac/MacTileLinkRx.scala

@@ -12,28 +12,21 @@ class RxFifo_Stream_Bundle extends Bundle{
 
 
 class MacTileLinkRxIO extends Bundle{
-    // val RxDataLatched2 = Output(UInt(8.W))
-    // val WriteRxDataToFifo = Output(Bool())
 
   val rxReq = Decoupled(new RxFifo_Stream_Bundle)
 
-  val RxAbortLatched = Output(Bool())
   val LatchedRxLength = Output(UInt(16.W))
   val RxStatusInLatched = Output( UInt(9.W) )
-  // val ShiftEnded_rck = Output(Bool())
 
   val RxLength = Input(UInt(16.W))
   val LoadRxStatus = Input(Bool())
       val RxStatusIn = Input(UInt(9.W))
-  // val ShiftEndedSyncb = Input(Bool())
+
-  val RxAbortSyncb = Input(Bool())
-  // val WriteRxDataToFifoSyncb = Input(Bool())
 
   val Busy_IRQ_rck = Output(Bool())
   val Busy_IRQ_syncb = Input(Bool())
 
   val RxData     = Input(UInt(8.W))      // Received data byte (from PHY)
-  val RxAbort    = Input(Bool())
   val RxValid    = Input(Bool())
   val RxReady    = Input(Bool())
   val RxStartFrm = Input(Bool())
@@ -46,7 +39,6 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
 
 
   val ShiftWillEnd = RegInit(false.B)
-  val RxAbortLatched = RegInit(false.B); io.RxAbortLatched := RxAbortLatched
 
   val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength   := LatchedRxLength
   val RxStatusInLatched = RegEnable(io.RxStatusIn, 0.U(9.W), io.LoadRxStatus); io.RxStatusInLatched := RxStatusInLatched
@@ -62,34 +54,14 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
     io.RxValid & io.RxReady & (io.RxStartFrm | RxEnableWindow )
 
 
-
-        // when(SetWriteRxDataToFifo & ~io.RxAbort){
-        //   WriteRxDataToFifo := true.B
-        //   RxDataLatched2 := io.RxData
-        // } .elsewhen(io.WriteRxDataToFifoSyncb | io.RxAbort){
-        //   WriteRxDataToFifo := false.B
-        // }
-
-    // // Generation of the end-of-frame signal
-    // when(SetWriteRxDataToFifo & ~io.RxAbort & io.RxEndFrm){
-    //   ShiftEnded_rck := true.B
-    // } .elsewhen(io.RxAbort | io.ShiftEndedSyncb & RegNext(io.ShiftEndedSyncb, false.B) ){
-    //   ShiftEnded_rck := false.B
-    // }
-
     // Generation of the end-of-frame signal
     when(io.RxStartFrm){
       RxEnableWindow := true.B
-    } .elsewhen(io.RxEndFrm | io.RxAbort){
+    } .elsewhen(io.RxEndFrm ){
       RxEnableWindow := false.B
     }
 
 
-    when(io.RxAbortSyncb){
-      RxAbortLatched := false.B
-    } .elsewhen(io.RxAbort){
-      RxAbortLatched := true.B
-    }
 
     when(io.RxValid & io.RxStartFrm & ~io.RxReady){
       Busy_IRQ_rck := true.B
@@ -99,7 +71,7 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
 
 
   val rxFifo = Module(new Queue(new RxFifo_Stream_Bundle, 4))
-  rxFifo.io.enq.valid := SetWriteRxDataToFifo & ~io.RxAbort
+  rxFifo.io.enq.valid := SetWriteRxDataToFifo
   rxFifo.io.enq.bits.data   := io.RxData
   rxFifo.io.enq.bits.isLast := io.RxEndFrm
   assert( ~(rxFifo.io.enq.valid & ~rxFifo.io.enq.ready) )

src/main/scala/Switch/mac/MacTilelink.scala

@@ -24,7 +24,6 @@ abstract class MacTileLinkBase() extends Module{
     val rxReq = Flipped(Decoupled(new RxFifo_Stream_Bundle))
     val rxResp = Decoupled(new Bool())
 
-    val RxAbortSync           = Input(Bool())
     val LatchedRxLength_rxclk = Input(UInt(16.W))
     val RxStatusInLatched_rxclk = Input(UInt(9.W))
     val RxReady = Output(Bool())
@@ -68,27 +67,26 @@ abstract class MacTileLinkBase() extends Module{
 
 
   val ShiftEndedSyncPluse         = io.rxReq.bits.isLast & io.rxReq.fire
-  val RxAbortPluse                = io.RxAbortSync             & ~RegNext(io.RxAbortSync, false.B)
 
   val RxReady = RegInit(false.B); io.RxReady := RxReady
 
 
   val rxBuffCtrlValid = RegInit(false.B)
   io.rxEnq.ctrl.valid := rxBuffCtrlValid
-  io.rxEnq.ctrl.bits.LatchedRxLength   := RegEnable(io.LatchedRxLength_rxclk,   ShiftEndedSyncPluse | RxAbortPluse)
+  io.rxEnq.ctrl.bits.LatchedRxLength   := RegEnable(io.LatchedRxLength_rxclk,   ShiftEndedSyncPluse )
-  io.rxEnq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
+  io.rxEnq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse )
-  io.rxEnq.ctrl.bits.isRxAbort         := RegEnable(RxAbortPluse,      false.B, ShiftEndedSyncPluse | RxAbortPluse)
+  
 
   when( io.rxEnq.ctrl.fire ){
     rxBuffCtrlValid := false.B
-  } .elsewhen( ShiftEndedSyncPluse | RxAbortPluse ){
+  } .elsewhen( ShiftEndedSyncPluse ){
     rxBuffCtrlValid := true.B
   }
 
 
 
   // RxReady generation
-  when(ShiftEndedSyncPluse | RxAbortPluse  ){
+  when(ShiftEndedSyncPluse ){
     RxReady := false.B
   } .elsewhen( io.r_RxEn & (io.rxEnq.data.ready) ){
     RxReady := true.B