159 lines
3.5 KiB
Scala
159 lines
3.5 KiB
Scala
package Switch
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import chisel3._
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import chisel3.util._
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class Receive_Enq_Ctrl_Bundle extends Bundle{
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val LatchedRxLength = UInt(16.W)
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val RxStatusInLatched = UInt(9.W)
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}
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class Receive_Deq_Ctrl_Bundle extends Receive_Enq_Ctrl_Bundle{
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}
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class Receive_Enq_Bundle extends Bundle{
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val data = Decoupled(UInt(8.W))
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val ctrl = Decoupled(new Receive_Enq_Ctrl_Bundle)
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}
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class Receive_Deq_Bundle extends Bundle{
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val data = Decoupled(UInt(8.W))
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val ctrl = Decoupled(new Receive_Deq_Ctrl_Bundle)
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val header = Decoupled(Vec( 20, UInt(8.W) ) )
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}
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class RxBuffIO extends Bundle{
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val enq = Flipped(new Receive_Enq_Bundle)
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val deq = new Receive_Deq_Bundle
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}
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class RxBuffBase extends Module{
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val io: RxBuffIO = IO(new RxBuffIO)
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val isEnqPi = RegInit(true.B)
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val isEnqPo = ~isEnqPi
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val isDeqPi = RegInit(true.B)
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val isDeqPo = ~isEnqPi
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val buff = for( i <- 0 until 2 ) yield { Module(new Queue( UInt(8.W), 2048 )) }
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val info = for( i <- 0 until 2 ) yield { Reg(new Receive_Enq_Ctrl_Bundle) }
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// dontTouch(buff(0).io.enq)
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// dontTouch(info(0))
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// dontTouch(buff(1).io.enq)
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// dontTouch(info(1))
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val header = for( i <- 0 until 2 ) yield { Reg(Vec( 20, UInt(8.W) )) }
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val hValid = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val cValid = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val recCnt = RegInit(0.U(5.W))
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}
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trait RxBuffEnq{ this: RxBuffBase =>
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buff(0).io.enq.valid := isEnqPi & io.enq.data.valid
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buff(0).io.enq.bits := io.enq.data.bits
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buff(1).io.enq.valid := isEnqPo & io.enq.data.valid
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buff(1).io.enq.bits := io.enq.data.bits
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io.enq.data.ready := (isEnqPi & buff(0).io.enq.ready) | (isEnqPo & buff(1).io.enq.ready)
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io.enq.ctrl.ready := true.B
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when( io.enq.ctrl.fire ){
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isEnqPi := ~isEnqPi
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when( isEnqPi ){
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info(0) := io.enq.ctrl.bits
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} .elsewhen( isEnqPo ){
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info(1) := io.enq.ctrl.bits
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}
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}
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when( io.enq.ctrl.fire ){
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recCnt := 0.U
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} .elsewhen( io.enq.data.fire ){
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when( recCnt < 20.U ){
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recCnt := recCnt + 1.U
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when( isEnqPi ){
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header(0)(recCnt) := io.enq.data.bits
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} .elsewhen( isEnqPo ){
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header(1)(recCnt) := io.enq.data.bits
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} .otherwise{
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assert(false.B, "Assert Failed, Rx Under Run")
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}
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}.elsewhen( recCnt === 20.U ){
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recCnt := 21.U
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}
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}
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}
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trait RxBuffDeq{ this: RxBuffBase =>
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when( io.deq.header.fire ){
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when( isDeqPi ) { hValid(0) := false.B }
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when( isDeqPo ) { hValid(1) := false.B }
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} .elsewhen( io.enq.data.fire & recCnt === 20.U ){
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when( isEnqPi ) { hValid(0) := true.B }
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when( isEnqPo ) { hValid(1) := true.B }
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}
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when( io.deq.ctrl.fire ){
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isDeqPi := ~isDeqPi
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when( isDeqPi ) { cValid(0) := false.B }
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when( isDeqPo ) { cValid(1) := false.B }
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} .elsewhen( io.enq.ctrl.fire ){
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when( isEnqPi ) { cValid(0) := true.B }
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when( isEnqPo ) { cValid(1) := true.B }
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}
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when( isDeqPi ){
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io.deq.data <> buff(0).io.deq
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buff(1).io.deq.ready := false.B
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io.deq.header.valid := hValid(0)
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io.deq.header.bits := header(0)
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io.deq.ctrl.valid := cValid(0) & ~buff(0).io.deq.valid
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io.deq.ctrl.bits := info(0)
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} .otherwise{
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assert( isDeqPo )
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io.deq.data <> buff(1).io.deq
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buff(0).io.deq.ready := false.B
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io.deq.header.valid := hValid(1)
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io.deq.header.bits := header(1)
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io.deq.ctrl.valid := cValid(1) & ~buff(1).io.deq.valid
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io.deq.ctrl.bits := info(1)
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}
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}
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class RxBuff extends RxBuffBase with RxBuffEnq with RxBuffDeq{
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}
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