ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

同步采样spi改成1转4模式

Browse Source
This commit is contained in:
RuigeLee
2026-01-20 16:58:01 +08:00
parent 905c6b96cf
commit 8d18719587
1 changed files with 76 additions and 79 deletions
Download Patch File Download Diff File Expand all files Collapse all files

145
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -35,10 +35,11 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val csn = Wire(Bool())
//数据信号相对SCK的稳定应该由外部主机保证，因此认为SCK采样时刻，数据都是稳定正确的
val shiftSCK = ShiftRegisters(sck, 3, false.B, true.B)
val shiftCSn = ShiftRegisters(csn, 3, true.B, true.B)
val shiftMOSI = Wire(Bool())
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
@@ -60,7 +61,12 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val byteSel = RegInit(0.U(12.W))
val byteSelNext = RegNext(byteSel, 0.U(12.W))
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(2) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U
val spiLen = RegInit(2.U(12.W))
val spiLenTemp = RegInit(2.U(12.W))
val spiCnt = RegInit(0.U(12.W))
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(2) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U & (spiCnt < spiLen)
io.isEnR := (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U ) & (spiCnt <= spiLen)
io.dataw := exRegi
io.addrr := addrr
@@ -75,26 +81,59 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
spiCnt := 0.U
} .elsewhen( io.isEnR | io.isEnW ){
spiCnt := spiCnt + 1.U
}
class SSpiInterface extends SpiInterfaceBase{
val spi = IO(new SSPIInterfaceIO)
val shiftMOSI = ShiftRegisters(spi.mosi, 3, false.B, true.B)
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
spiLenTemp := 0.U
spiLen := 2.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 2.U){ //CS为低，且SCK上跳的第0byte
spiLenTemp := Cat( exRegi(2,0), shiftMOSI, 0.U(8.W) )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 3.U) {//CS为低，且SCK上跳的第0byte
spiLenTemp := Cat(spiLenTemp(11,8), exRegi(6,0), shiftMOSI)
spiLen := Cat(spiLenTemp(11,8), exRegi(6,0), shiftMOSI)
}
sck := spi.sck
csn := spi.csn
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrr := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrr := Cat( exRegi(6,0), shiftMOSI )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI)
} .otherwise{ // byteSel > 1.U
when( isSckPosedge & byteSel >= 3.U & bitSel === 0.U ){
addrr := addrr + 1.U
}
}
io.isEnR :=
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === 1.U & byteSel === 2.U ) |
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U )
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrw := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrw := Cat( exRegi(6,0), shiftMOSI )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrw := Cat(addrw(7,0), exRegi(6,0), shiftMOSI )
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(0) & byteSelNext >= 4.U & bitSelNext.andR ){
addrw := addrw + 1.U
}
}
when( shiftCSn(2) & ~shiftCSn(1) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
spiCmd := 0.U
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := shiftMOSI(1)
spiCmd := shiftMOSI
}
}
class SSpiInterface extends SpiInterfaceBase{
val spi = IO(new SSPIInterfaceIO)
shiftMOSI := ShiftRegister(spi.mosi, 2, false.B, true.B)
sck := spi.sck
csn := spi.csn
spi.miso := exRego.extract(7)
when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -106,9 +145,9 @@ class SSpiInterface extends SpiInterfaceBase{
//输入看SCK上升沿
when( isSckPosedge & ~shiftCSn(1) ){
when( bitSel === 0.U ){
exRegi := Cat( 0.U, shiftMOSI(1) )
exRegi := Cat( 0.U, shiftMOSI )
}.otherwise{
exRegi := Cat( exRegi(6,0), shiftMOSI(1) )
exRegi := Cat( exRegi(6,0), shiftMOSI )
}
}
@@ -117,7 +156,7 @@ class SSpiInterface extends SpiInterfaceBase{
exRego := 0.U //第一个byte 地址0
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
when( bitSel.andR ){
when((byteSel === 0.U || byteSel === 1.U) ){
when((byteSel === 0.U || byteSel === 1.U || byteSel === 2.U || byteSel === 3.U ) ){
exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){
exRego := io.datar
@@ -127,35 +166,12 @@ class SSpiInterface extends SpiInterfaceBase{
}
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrr := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrr := Cat( exRegi(6,0), shiftMOSI(1) )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI(1))
} .otherwise{ // byteSel > 1.U
when( isSckPosedge & byteSel >= 2.U & bitSel === 0.U ){
addrr := addrr + 1.U
}
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrw := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrw := Cat( exRegi(6,0), shiftMOSI(1) )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrw := Cat(addrw(7,0), exRegi(6,0), shiftMOSI(1) )
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(0) & byteSelNext >= 3.U & bitSelNext.andR ){
addrw := addrw + 1.U
}
}
}
class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
val qspi = IO(new QSPIInterfaceIO)
val shiftMOSI = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)
val shiftDat = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)
shiftMOSI := shiftDat(1).extract(0)
sck := qspi.sck
csn := qspi.csn
@@ -163,31 +179,35 @@ class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
qspi.isDirIn := ~isSpiRead
io.isEnR :=
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & shiftMOSI(1) === "b1000".U & byteSel === 2.U ) |
(isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
when( (shiftCSn(2) & ~shiftCSn(1)) || (~shiftCSn(2) & shiftCSn(1)) ){ //CS下跳或上跳
spiCmd := 0.U
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := shiftMOSI(1).extract(3)
}
when( shiftCSn(2) & ~shiftCSn(1) ){
bitSel := 0.U
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
when( byteSel <= 3.U ){
bitSel := bitSel + 1.U
} .otherwise{
bitSel := ~bitSel
}
}
//输入看SCK上升沿
when( isSckPosedge & ~shiftCSn(1) ){
when( byteSel <= 3.U ){
when( bitSel === 0.U ){
exRegi := Cat( 0.U, shiftMOSI(1) )
exRegi := Cat( 0.U, shiftMOSI )
}.otherwise{
exRegi := Cat( exRegi(3,0), shiftMOSI(1) )
exRegi := Cat( exRegi(6,0), shiftMOSI )
}
} .otherwise{
when( bitSel === 0.U ){
exRegi := Cat( 0.U, shiftDat(1) )
}.otherwise{
exRegi := Cat( exRegi(3,0), shiftDat(1) )
}
}
}
@@ -199,7 +219,7 @@ class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
& ~shiftCSn(1)
){
when( (if( edge ) { bitSel.andR } else { bitSel === 0.U }) ){
when( byteSel === 0.U || byteSel === 1.U || ( if( edge ) { false.B } else { byteSel === 2.U } ) ){
when( byteSel === 0.U || byteSel === 1.U || byteSel === 2.U || ( if( edge ) { false.B } else { byteSel === 3.U } ) ){
exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){
exRego := io.datar
@@ -210,29 +230,6 @@ class QSpiInterface(edge: Boolean) extends SpiInterfaceBase{
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrr := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrr := Cat( exRegi(3,0), shiftMOSI(1) )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(addrr(7,0), exRegi(3,0), shiftMOSI(1))
} .otherwise{ // byteSel > 1.U
when( isSckPosedge & byteSel >= 2.U & bitSel === 0.U ){
addrr := addrr + 1.U
}
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrw := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrw := Cat( exRegi(3,0), shiftMOSI(1) )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrw := Cat(addrw(7,0), exRegi(3,0), shiftMOSI(1) )
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(0) & byteSelNext >= 3.U & bitSelNext.andR ){
addrw := addrw + 1.U
}
}
}