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写死16相位

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Merge branch 'mp_eb_dev' into feature/multiPhaseCDRIn

# Conflicts:
#	src/main/scala/backBoard/ebus/CDRIn.scala
#	src/main/scala/backBoard/shin/ShinTop.scala
#	tb/shinTest/ShinTopSpiTb.v
This commit is contained in:
Ruige Lee
2025-08-05 16:49:41 +08:00
parent dc96f16e45 9f88d26ba1
commit 8c09a6c4aa
5 changed files with 233 additions and 79 deletions
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157
src/main/scala/backBoard/ebus/CDRIn.scala
View File

@@ -8,24 +8,29 @@ import chisel3.util._
class CDRInIO extends Bundle{
val axis = Decoupled(new AXIS_Bundle(8))
val serDat = Input(Bool())
val overCLK = Input(Bool())
}
abstract class CDRInBase extends Module{
def sampleRate: Int = 4
val io: CDRInIO = IO(new CDRInIO)
val syncSerDat = Wire(Bool())
}
trait CDRInOverSample{ this: CDRInBase =>
val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate+3 ) }
val overCLK = IO(Input(Bool()))
val sampleRate: Int = 4
require(sampleRate >= 4)
val sampleReg = withClockAndReset(overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate+3 ) }
val flitReg = for( i <- 0 until sampleRate ) yield {
withClockAndReset(io.overCLK.asClock, reset.asBool){
withClockAndReset(overCLK.asClock, reset.asBool){
RegNext(
(sampleReg(i) & sampleReg(i+1)) |
(sampleReg(i) & sampleReg(i+2)) |
@@ -34,59 +39,19 @@ trait CDRInOverSample{ this: CDRInBase =>
}
}
// val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
// val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
// val isArbLock = RegInit(false.B)
// for( i <- 0 until sampleRate ){
// arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) )
// when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){
// isArbLock := true.B
// arbSel := i.U
// }
// }
// when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){
// isArbLock := false.B
// }
// val syncSerDat =
// Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
val arbCnt = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
withClockAndReset(io.overCLK.asClock, reset.asBool){
val arbLock = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
withClockAndReset(overCLK.asClock, reset.asBool){
when( flitReg(0) ^ flitReg(1) ){
arbLock := arbCnt
}
}
val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext(
val asyncSerDat = withClockAndReset(overCLK.asClock, reset.asBool){ RegNext(
Mux1H(
// Seq(
// //(arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3),
// (arbLock === (1.U << 0) & arbCnt === (1.U << 0)) -> sampleReg(3),
// (arbLock === (1.U << 0) & arbCnt === (1.U << 1)) -> sampleReg(0),
// (arbLock === (1.U << 0) & arbCnt === (1.U << 2)) -> sampleReg(1),
// (arbLock === (1.U << 0) & arbCnt === (1.U << 3)) -> sampleReg(2),
// (arbLock === (1.U << 1) & arbCnt === (1.U << 0)) -> sampleReg(2),
// (arbLock === (1.U << 1) & arbCnt === (1.U << 1)) -> sampleReg(3),
// (arbLock === (1.U << 1) & arbCnt === (1.U << 2)) -> sampleReg(0),
// (arbLock === (1.U << 1) & arbCnt === (1.U << 3)) -> sampleReg(1),
// (arbLock === (1.U << 2) & arbCnt === (1.U << 0)) -> sampleReg(1),
// (arbLock === (1.U << 2) & arbCnt === (1.U << 1)) -> sampleReg(2),
// (arbLock === (1.U << 2) & arbCnt === (1.U << 2)) -> sampleReg(3),
// (arbLock === (1.U << 2) & arbCnt === (1.U << 3)) -> sampleReg(0),
// (arbLock === (1.U << 3) & arbCnt === (1.U << 0)) -> sampleReg(0),
// (arbLock === (1.U << 3) & arbCnt === (1.U << 1)) -> sampleReg(1),
// (arbLock === (1.U << 3) & arbCnt === (1.U << 2)) -> sampleReg(2),
// (arbLock === (1.U << 3) & arbCnt === (1.U << 3)) -> sampleReg(3),
// )
(for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield {
//跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值
((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> flitReg((sampleRate + 2 - i + j) % sampleRate)
@@ -95,13 +60,88 @@ trait CDRInOverSample{ this: CDRInBase =>
)}
val syncSerDat = ShiftRegister( asyncSerDat, 2 )
syncSerDat := ShiftRegister( asyncSerDat, 2 )
}
trait CDRInMultiSample{ this: CDRInBase =>
val clkNum: Int = 16
//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
val multiCLK = IO(Input(Vec(16, Bool())))
// val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
val sampleReg = for( i <- 0 until 16 ) yield {
withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
}
val flitReg = for( i <- 0 until 16 ) yield {
if( i == 0 ) {
(sampleReg(15) & sampleReg(0)) |
(sampleReg(15) & sampleReg(1)) |
(sampleReg(0) & sampleReg(1))
} else if ( i > 0 && i < 15 ){
(sampleReg(i-1) & sampleReg(i)) |
(sampleReg(i-1) & sampleReg(i+1)) |
(sampleReg(i) & sampleReg(i+1))
} else// ( i == 15 )
(sampleReg(14) & sampleReg(15)) |
(sampleReg(14) & sampleReg(0)) |
(sampleReg(15) & sampleReg(0))
}
val arbLock = Reg(UInt( 16.W ))
//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
when( flitReg(0) ^ flitReg(1) ){
arbLock := "b1".U(16.W) << 2
} .elsewhen( flitReg(1) ^ flitReg(2) ){
arbLock := "b1".U(16.W) << 3
} .elsewhen( flitReg(2) ^ flitReg(3) ){
arbLock := "b1".U(16.W) << 4
} .elsewhen( flitReg(3) ^ flitReg(4) ){
arbLock := "b1".U(16.W) << 5
} .elsewhen( flitReg(4) ^ flitReg(5) ){
arbLock := "b1".U(16.W) << 6
} .elsewhen( flitReg(5) ^ flitReg(6) ){
arbLock := "b1".U(16.W) << 7
} .elsewhen( flitReg(6) ^ flitReg(7) ){
arbLock := "b1".U(16.W) << 8
} .elsewhen( flitReg(7) ^ flitReg(8) ){
arbLock := "b1".U(16.W) << 9
} .elsewhen( flitReg(8) ^ flitReg(9) ){
arbLock := "b1".U(16.W) << 10
} .elsewhen( flitReg(9) ^ flitReg(10) ){
arbLock := "b1".U(16.W) << 11
} .elsewhen( flitReg(10) ^ flitReg(11) ){
arbLock := "b1".U(16.W) << 12
} .elsewhen( flitReg(11) ^ flitReg(12) ){
arbLock := "b1".U(16.W) << 13
} .elsewhen( flitReg(12) ^ flitReg(13) ){
arbLock := "b1".U(16.W) << 14
} .elsewhen( flitReg(13) ^ flitReg(14) ){
arbLock := "b1".U(16.W) << 15
} .elsewhen( flitReg(14) ^ flitReg(15) ){
arbLock := "b1".U(16.W) << 0
} .elsewhen( flitReg(15) ^ flitReg(0) ){
arbLock := "b1".U(16.W) << 1
}
val asyncSerDat =
Mux1H(
(for { i <- 0 until clkNum } yield {
(arbLock === (1.U << i)) -> flitReg(i)
})
)
syncSerDat := ShiftRegister( asyncSerDat, 2 )
}
trait CDRInAxis{ this: CDRInBase =>
@@ -120,7 +160,6 @@ trait CDRInAxis{ this: CDRInBase =>
val bitCnt = Reg(UInt(4.W))
val byteCnt = RegInit(0.U((12+1).W))
val syncSerDat: Bool
val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
val shiftData = Dualb4b5Decoder(checkSFD(9,0))
@@ -188,6 +227,10 @@ trait CDRInAxis{ this: CDRInBase =>
}
class CDRIn extends CDRInBase
with CDRInAxis
with CDRInOverSample
class CDRIn extends CDRInBase with CDRInOverSample with CDRInAxis
class MPCDRIn extends CDRInBase
with CDRInAxis
with CDRInMultiSample

9
src/main/scala/backBoard/ebus/RoCC2CDR.scala
View File

@@ -54,12 +54,17 @@ abstract class RoCC2CDRImplBase(outer: RoCC2CDR)(implicit p: Parameters) extends
val cdrOutio = IO(Output(new RocCC2CDROutIO))
val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
when(true.B){
print("Warning!!! New Code has not been reviewed!\n")
}
CDRIn(0).io.serDat := cdrInio.dDatIn
CDRIn(1).io.serDat := cdrInio.uDatIn
CDRIn(0).io.overCLK := cdrInio.overCLK
CDRIn(1).io.overCLK := cdrInio.overCLK
CDRIn(0).overCLK := cdrInio.overCLK
CDRIn(1).overCLK := cdrInio.overCLK
val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }

7
src/main/scala/backBoard/ebus/TL2CDR.scala
View File

@@ -56,12 +56,15 @@ abstract class TL2CDRImplBase(outer: TL2CDR)(implicit p: Parameters) extends Laz
val ( bus, edge ) = outer.node.in.head
val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
when(true.B){
print("Warning!!! New Code has not been reviewed!\n")
}
CDRIn(0).io.serDat := io.dDatIn
CDRIn(1).io.serDat := io.uDatIn
CDRIn(0).io.overCLK := io.overCLK
CDRIn(1).io.overCLK := io.overCLK
CDRIn(0).overCLK := io.overCLK
CDRIn(1).overCLK := io.overCLK
val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }

28
src/main/scala/backBoard/shin/ShinTop.scala
View File

@@ -5,20 +5,21 @@ import chisel3.util._
class ShinTopIO extends Bundle{
val clk8x = Input(Bool())
val dDatIn = Input(Bool())
val dDatOut = Output(Bool())
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
val multiCLK = Input(Vec(16, Bool()))
val iqspi = new QSPIInterfaceIO
val ospi = new SSPIInterfaceIO
val oqspi = new QSPIInterfaceIO
val rsp = Valid(new Bundle{
val isError = Bool()
})
// val rsp = Valid(new Bundle{
// val isError = Bool()
// })
val iSync = Output(Vec(4, Bool()))
val oSync = Output(Vec(4, Bool()))
@@ -37,13 +38,20 @@ class ShinTopIO extends Bundle{
abstract class ShinTopBase extends Module{
val io: ShinTopIO = IO(new ShinTopIO)
val slaveParser = Module(new SlaveParser )
val masterParser = Module(new MasterParser)
val downCDRIn = Module(new CDRIn)
val upCDRIn = Module(new CDRIn)
val downCDRIn = Module(new MPCDRIn)
val upCDRIn = Module(new MPCDRIn)
downCDRIn.multiCLK := io.multiCLK
upCDRIn.multiCLK := io.multiCLK
val downCDROut = Module(new CDROut)
val upCDROut = Module(new CDROut)
@@ -61,12 +69,6 @@ abstract class ShinTopBase extends Module{
io.isSoftReset := interface.io.isSoftReset
io.interrupt := interface.io.interrupt
downCDRIn.io.overCLK := io.clk8x
upCDRIn.io.overCLK := io.clk8x
io.ospi <> interface.io.ospi
io.iqspi <> interface.io.iqspi
io.oqspi <> interface.io.oqspi
@@ -288,7 +290,7 @@ trait ShinTopMaster{ this: ShinTopBase =>
masterParser.io.req := interface.io.txReq.valid
// masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
io.rsp := masterParser.io.rsp
// io.rsp := masterParser.io.rsp
masterParser.io.cReg := interface.io.cReg
masterParser.io.mReg := interface.io.mReg

111
tb/shinTest/ShinTopSpiTb.v
View File

@@ -38,6 +38,8 @@ module ShinTopSpiTb(
reg reset;
reg clk8x;
reg [15:0] multiCLK;
wire [3:0] dDat_w;
wire [3:0] uDat_w;
@@ -65,15 +67,34 @@ module ShinTopSpiTb(
wire [4:0] io_int_sig;
reg _reset_deadline_ind;
reg _deadline_ind;
reg[31:0] _deadline_ind_ctr;
ShinTop s_ShinTop_Mst(
.clock(clock),
.reset(reset | isSoftReset[0]),
.io_clk8x(clk8x),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
.io_multiCLK_2(multiCLK[2]),
.io_multiCLK_3(multiCLK[3]),
.io_multiCLK_4(multiCLK[4]),
.io_multiCLK_5(multiCLK[5]),
.io_multiCLK_6(multiCLK[6]),
.io_multiCLK_7(multiCLK[7]),
.io_multiCLK_8(multiCLK[8]),
.io_multiCLK_9(multiCLK[9]),
.io_multiCLK_10(multiCLK[10]),
.io_multiCLK_11(multiCLK[11]),
.io_multiCLK_12(multiCLK[12]),
.io_multiCLK_13(multiCLK[13]),
.io_multiCLK_14(multiCLK[14]),
.io_multiCLK_15(multiCLK[15]),
.io_dDatIn(1'b0),
.io_dDatOut(dDat_w[0]),
.io_uDatIn(uDat_w[0]),
@@ -107,7 +128,23 @@ ShinTop s_ShinTop_slv0(
.clock(clock),
.reset(reset | isSoftReset[1]),
.io_clk8x(clk8x),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
.io_multiCLK_2(multiCLK[2]),
.io_multiCLK_3(multiCLK[3]),
.io_multiCLK_4(multiCLK[4]),
.io_multiCLK_5(multiCLK[5]),
.io_multiCLK_6(multiCLK[6]),
.io_multiCLK_7(multiCLK[7]),
.io_multiCLK_8(multiCLK[8]),
.io_multiCLK_9(multiCLK[9]),
.io_multiCLK_10(multiCLK[10]),
.io_multiCLK_11(multiCLK[11]),
.io_multiCLK_12(multiCLK[12]),
.io_multiCLK_13(multiCLK[13]),
.io_multiCLK_14(multiCLK[14]),
.io_multiCLK_15(multiCLK[15]),
.io_dDatIn(dDat_w[0]),
.io_dDatOut(dDat_w[1]),
.io_uDatIn(uDat_w[1]),
@@ -140,7 +177,23 @@ ShinTop s_ShinTop_slv1(
.clock(clock),
.reset(reset | isSoftReset[2]),
.io_clk8x(clk8x),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
.io_multiCLK_2(multiCLK[2]),
.io_multiCLK_3(multiCLK[3]),
.io_multiCLK_4(multiCLK[4]),
.io_multiCLK_5(multiCLK[5]),
.io_multiCLK_6(multiCLK[6]),
.io_multiCLK_7(multiCLK[7]),
.io_multiCLK_8(multiCLK[8]),
.io_multiCLK_9(multiCLK[9]),
.io_multiCLK_10(multiCLK[10]),
.io_multiCLK_11(multiCLK[11]),
.io_multiCLK_12(multiCLK[12]),
.io_multiCLK_13(multiCLK[13]),
.io_multiCLK_14(multiCLK[14]),
.io_multiCLK_15(multiCLK[15]),
.io_dDatIn(dDat_w[1]),
.io_dDatOut(dDat_w[2]),
.io_uDatIn(uDat_w[2]),
@@ -173,7 +226,23 @@ ShinTop s_ShinTop_slv2(
.clock(clock),
.reset(reset | isSoftReset[3]),
.io_clk8x(clk8x),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
.io_multiCLK_2(multiCLK[2]),
.io_multiCLK_3(multiCLK[3]),
.io_multiCLK_4(multiCLK[4]),
.io_multiCLK_5(multiCLK[5]),
.io_multiCLK_6(multiCLK[6]),
.io_multiCLK_7(multiCLK[7]),
.io_multiCLK_8(multiCLK[8]),
.io_multiCLK_9(multiCLK[9]),
.io_multiCLK_10(multiCLK[10]),
.io_multiCLK_11(multiCLK[11]),
.io_multiCLK_12(multiCLK[12]),
.io_multiCLK_13(multiCLK[13]),
.io_multiCLK_14(multiCLK[14]),
.io_multiCLK_15(multiCLK[15]),
.io_dDatIn(dDat_w[2]),
.io_dDatOut(dDat_w[3]),
.io_uDatIn(uDat_w[3]),
@@ -206,7 +275,23 @@ ShinTop s_ShinTop_slv3(
.clock(clock),
.reset(reset | isSoftReset[4]),
.io_clk8x(clk8x),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
.io_multiCLK_2(multiCLK[2]),
.io_multiCLK_3(multiCLK[3]),
.io_multiCLK_4(multiCLK[4]),
.io_multiCLK_5(multiCLK[5]),
.io_multiCLK_6(multiCLK[6]),
.io_multiCLK_7(multiCLK[7]),
.io_multiCLK_8(multiCLK[8]),
.io_multiCLK_9(multiCLK[9]),
.io_multiCLK_10(multiCLK[10]),
.io_multiCLK_11(multiCLK[11]),
.io_multiCLK_12(multiCLK[12]),
.io_multiCLK_13(multiCLK[13]),
.io_multiCLK_14(multiCLK[14]),
.io_multiCLK_15(multiCLK[15]),
.io_dDatIn(dDat_w[3]),
.io_dDatOut(),
.io_uDatIn(1'b0),
@@ -281,6 +366,22 @@ initial begin
forever begin #80 clock <= ~clock; end
end
generate
for( genvar i = 0; i < 16; i = i + 1 ) begin
initial begin
multiCLK[i] = 0;
for( integer j = 0; j < i; j = j + 1 ) begin
#20
;
end
forever begin #80 multiCLK[i] <= ~multiCLK[i]; end
end
end
endgenerate
initial
begin
spidata_file = $fopen("spi_trans_data.txt", "w");