From 1319027c9e0e2a17b9f01d3abad74a38261c7fb5 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 17 Jul 2025 17:22:08 +0800 Subject: [PATCH 1/6] =?UTF-8?q?=E4=BB=A3=E7=A0=81=E6=B8=85=E7=90=86?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 44 ----------------------- 1 file changed, 44 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index fae6248..ced0ef3 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -28,27 +28,6 @@ abstract class CDRInBase extends Module{ trait CDRInOverSample{ this: CDRInBase => val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) } - - - // val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) } - // val arbSel = Reg(UInt( log2Ceil(sampleRate).W )) - // val isArbLock = RegInit(false.B) - - // for( i <- 0 until sampleRate ){ - // arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) ) - // when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){ - // isArbLock := true.B - // arbSel := i.U - // } - // } - - // when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){ - // isArbLock := false.B - // } - - // val syncSerDat = - // Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } ) - val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) } arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) ) val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) } @@ -58,29 +37,6 @@ trait CDRInOverSample{ this: CDRInBase => val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext( Mux1H( - // Seq( - // //(arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3), - // (arbLock === (1.U << 0) & arbCnt === (1.U << 0)) -> sampleReg(3), - // (arbLock === (1.U << 0) & arbCnt === (1.U << 1)) -> sampleReg(0), - // (arbLock === (1.U << 0) & arbCnt === (1.U << 2)) -> sampleReg(1), - // (arbLock === (1.U << 0) & arbCnt === (1.U << 3)) -> sampleReg(2), - - // (arbLock === (1.U << 1) & arbCnt === (1.U << 0)) -> sampleReg(2), - // (arbLock === (1.U << 1) & arbCnt === (1.U << 1)) -> sampleReg(3), - // (arbLock === (1.U << 1) & arbCnt === (1.U << 2)) -> sampleReg(0), - // (arbLock === (1.U << 1) & arbCnt === (1.U << 3)) -> sampleReg(1), - - // (arbLock === (1.U << 2) & arbCnt === (1.U << 0)) -> sampleReg(1), - // (arbLock === (1.U << 2) & arbCnt === (1.U << 1)) -> sampleReg(2), - // (arbLock === (1.U << 2) & arbCnt === (1.U << 2)) -> sampleReg(3), - // (arbLock === (1.U << 2) & arbCnt === (1.U << 3)) -> sampleReg(0), - - // (arbLock === (1.U << 3) & arbCnt === (1.U << 0)) -> sampleReg(0), - // (arbLock === (1.U << 3) & arbCnt === (1.U << 1)) -> sampleReg(1), - // (arbLock === (1.U << 3) & arbCnt === (1.U << 2)) -> sampleReg(2), - // (arbLock === (1.U << 3) & arbCnt === (1.U << 3)) -> sampleReg(3), - // ) - (for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield { //跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值 ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((sampleRate - 1 - i + j) % sampleRate) From bf8fce2671b155962f1238a0b967c1aa0cca04e9 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 17 Jul 2025 17:47:59 +0800 Subject: [PATCH 2/6] =?UTF-8?q?=E9=9C=80=E8=A6=81=E8=80=83=E8=99=91?= =?UTF-8?q?=E5=A4=9A=E9=A1=B9=E4=BD=8D=E6=97=B6=E9=92=9F=E6=98=AF=E6=8C=89?= =?UTF-8?q?=E5=90=8C=E6=AD=A5=E6=97=B6=E9=92=9F=E8=BF=98=E6=98=AF=E5=BC=82?= =?UTF-8?q?=E6=AD=A5=E6=97=B6=E9=92=9F=E5=A4=84=E7=90=86?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 50 +++++++++++++++++++++-- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index ced0ef3..7605471 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -47,11 +47,55 @@ trait CDRInOverSample{ this: CDRInBase => val syncSerDat = ShiftRegister( asyncSerDat, 2 ) - - - } +trait CDRInMultiSample{ this: CDRInBase => + val clkNum: Int = 16 + // val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) } + val sampleReg = for( i <- 0 until clkNum ) yield { + withClockAndReset(io.multiCLK(i).asClock, reset.asBool){ ShiftRegisters( io.serDat, 2 ) } + } + + // val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) } + // arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) ) + val arbCnt = RegInit("b1".U(clkNum.W)) + arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(clkNum-1) ) + + // val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) } + // when( sampleReg(0) ^ sampleReg(1) ){ + // arbLock := arbCnt + // } + val arbLock = Reg(UInt( clkNum.W )) + when( sampleReg(0) ^ sampleReg(1) ){ + arbLock := arbCnt + } + + + // val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext( + // Mux1H( + // (for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield { + // //跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值 + // ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((sampleRate - 1 - i + j) % sampleRate) + // }) + // ) + // )} + + val asyncSerDat = + Mux1H( + (for { i <- 0 until clkNum; j <- 0 until clkNum } yield { + //跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值 + ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((clkNum - 1 - i + j) % clkNum) + }) + ) + + + + // val syncSerDat = ShiftRegister( asyncSerDat, 2 ) + val syncSerDat = ShiftRegister( asyncSerDat, 2 ) + +} + + trait CDRInAxis{ this: CDRInBase => From 7c632c8c1bf76493327f4663f2f29d5ada1bb017 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 22 Jul 2025 09:35:06 +0800 Subject: [PATCH 3/6] =?UTF-8?q?=E7=BC=96=E8=AF=91=E9=80=9A=E8=BF=87?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 36 ++++++++++------ src/main/scala/backBoard/ebus/RoCC2CDR.scala | 11 +++-- src/main/scala/backBoard/ebus/TL2CDR.scala | 9 ++-- src/main/scala/backBoard/shin/ShinTop.scala | 43 ++++++++++++++++---- 4 files changed, 73 insertions(+), 26 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 7605471..5d9b192 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -8,14 +8,13 @@ import chisel3.util._ class CDRInIO extends Bundle{ val axis = Decoupled(new AXIS_Bundle(8)) val serDat = Input(Bool()) - val overCLK = Input(Bool()) val initEncryptor = Flipped(Valid(UInt(128.W))) } abstract class CDRInBase extends Module{ - def sampleRate: Int = 4 + val io: CDRInIO = IO(new CDRInIO) @@ -23,19 +22,24 @@ abstract class CDRInBase extends Module{ encryptor.io.init := io.initEncryptor encryptor.io.op.ready := io.axis.fire + val syncSerDat = Wire(Bool()) } trait CDRInOverSample{ this: CDRInBase => - val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) } + val overCLK = IO(Input(Bool())) + val sampleRate: Int = 4 + require(sampleRate >= 4) - val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) } + val sampleReg = withClockAndReset(overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) } + + val arbCnt = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) } arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) ) - val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) } + val arbLock = withClockAndReset(overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) } when( sampleReg(0) ^ sampleReg(1) ){ arbLock := arbCnt } - val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext( + val asyncSerDat = withClockAndReset(overCLK.asClock, reset.asBool){ RegNext( Mux1H( (for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield { //跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值 @@ -45,21 +49,27 @@ trait CDRInOverSample{ this: CDRInBase => )} - val syncSerDat = ShiftRegister( asyncSerDat, 2 ) + syncSerDat := ShiftRegister( asyncSerDat, 2 ) } trait CDRInMultiSample{ this: CDRInBase => - val clkNum: Int = 16 + + val clkNum: Int = 8 + require(clkNum >= 4) + + //multiCLK 需要按照超前相位接线，即0为最后到达，1次后 + val multiCLK = IO(Input(Vec(clkNum, Bool()))) + // val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) } val sampleReg = for( i <- 0 until clkNum ) yield { - withClockAndReset(io.multiCLK(i).asClock, reset.asBool){ ShiftRegisters( io.serDat, 2 ) } + withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) } } // val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) } // arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) ) val arbCnt = RegInit("b1".U(clkNum.W)) - arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(clkNum-1) ) + arbCnt := Cat( arbCnt(clkNum-2,0), arbCnt.extract(clkNum-1) ) // val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) } // when( sampleReg(0) ^ sampleReg(1) ){ @@ -91,7 +101,7 @@ trait CDRInMultiSample{ this: CDRInBase => // val syncSerDat = ShiftRegister( asyncSerDat, 2 ) - val syncSerDat = ShiftRegister( asyncSerDat, 2 ) + syncSerDat := ShiftRegister( asyncSerDat, 2 ) } @@ -114,7 +124,6 @@ trait CDRInAxis{ this: CDRInBase => val bitCnt = Reg(UInt(4.W)) val byteCnt = RegInit(0.U((12+1).W)) - val syncSerDat: Bool val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat ) val shiftData = Dualb4b5Decoder(checkSFD(9,0)) @@ -183,5 +192,6 @@ trait CDRInAxis{ this: CDRInBase => } -class CDRIn extends CDRInBase with CDRInOverSample with CDRInAxis +class CDRIn extends CDRInBase +with CDRInAxis diff --git a/src/main/scala/backBoard/ebus/RoCC2CDR.scala b/src/main/scala/backBoard/ebus/RoCC2CDR.scala index 701c041..d03a515 100644 --- a/src/main/scala/backBoard/ebus/RoCC2CDR.scala +++ b/src/main/scala/backBoard/ebus/RoCC2CDR.scala @@ -53,13 +53,18 @@ abstract class RoCC2CDRImplBase(outer: RoCC2CDR)(implicit p: Parameters) extends val cdrInio = IO(Input(new RocCC2CDRInIO)) val cdrOutio = IO(Output(new RocCC2CDROutIO)) - val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) } + val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn with CDRInOverSample) } + when(true.B){ + print("Warning!!! New Code has not been reviewed!\n") + } CDRIn(0).io.serDat := cdrInio.dDatIn CDRIn(1).io.serDat := cdrInio.uDatIn - CDRIn(0).io.overCLK := cdrInio.overCLK - CDRIn(1).io.overCLK := cdrInio.overCLK + CDRIn(0).overCLK := cdrInio.overCLK + CDRIn(1).overCLK := cdrInio.overCLK + + val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) } diff --git a/src/main/scala/backBoard/ebus/TL2CDR.scala b/src/main/scala/backBoard/ebus/TL2CDR.scala index 103e95e..ddfe29a 100644 --- a/src/main/scala/backBoard/ebus/TL2CDR.scala +++ b/src/main/scala/backBoard/ebus/TL2CDR.scala @@ -55,13 +55,16 @@ abstract class TL2CDRImplBase(outer: TL2CDR)(implicit p: Parameters) extends Laz val ( int, _ ) = outer.int_node.out(0) val ( bus, edge ) = outer.node.in.head - val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) } + val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn with CDRInOverSample) } + when(true.B){ + print("Warning!!! New Code has not been reviewed!\n") + } CDRIn(0).io.serDat := io.dDatIn CDRIn(1).io.serDat := io.uDatIn - CDRIn(0).io.overCLK := io.overCLK - CDRIn(1).io.overCLK := io.overCLK + CDRIn(0).overCLK := io.overCLK + CDRIn(1).overCLK := io.overCLK val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) } diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 9f210f0..589023f 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -5,7 +5,6 @@ import chisel3.util._ class ShinTopIO extends Bundle{ - val clk8x = Input(Bool()) val dDatIn = Input(Bool()) val dDatOut = Output(Bool()) @@ -56,18 +55,50 @@ class ShinTopIO extends Bundle{ abstract class ShinTopBase extends Module{ + def isMultiCLK: Int = 8 + val io: ShinTopIO = IO(new ShinTopIO) - // val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) } - // val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) } + + val slaveParser = Module(new SlaveParser ) val masterParser = Module(new MasterParser) - val downCDRIn = Module(new CDRIn) - val upCDRIn = Module(new CDRIn) + val ( downCDRIn, upCDRIn ) = + if( isMultiCLK == 0 ){ + val clk8x = IO(Input(Bool())) + val down = Module(new CDRIn with CDRInOverSample ) + val up = Module(new CDRIn with CDRInOverSample ) + down.overCLK := clk8x + up.overCLK := clk8x + (down, up) + } else{ + val multiCLK = IO(Input(Vec(isMultiCLK, Bool()))) + val down = Module(new CDRIn with CDRInMultiSample) + val up = Module(new CDRIn with CDRInMultiSample) + down.multiCLK := multiCLK + up.multiCLK := multiCLK + (down, up) + } + + + // val downCDRIn = if( isMultiCLK == 0 ) { Module(new CDRIn with CDRInOverSample ) } else { Module(new CDRIn with CDRInMultiSample) } + // val upCDRIn = if( isMultiCLK == 0 ) { Module(new CDRIn with CDRInOverSample ) } else { Module(new CDRIn with CDRInMultiSample) } + + // if( isMultiCLK == 0 ){ + // val clk8x = IO(Input(Bool())) + // downCDRIn.overCLK := clk8x + // upCDRIn.overCLK := clk8x + // } else { + // val multiCLK = IO(Input(Vec(isMultiCLK, Bool()))) + // downCDRIn.multiCLK := multiCLK + // upCDRIn.multiCLK := multiCLK + // } + + val downCDROut = Module(new CDROut) val upCDROut = Module(new CDROut) @@ -79,11 +110,9 @@ abstract class ShinTopBase extends Module{ io.interrupt := interface.io.interrupt downCDRIn.io.serDat := io.dDatIn - downCDRIn.io.overCLK := io.clk8x downCDRIn.io.initEncryptor := interface.io.initEncryptor upCDRIn.io.serDat := io.uDatIn - upCDRIn.io.overCLK := io.clk8x upCDRIn.io.initEncryptor := interface.io.initEncryptor io.dDatOut := downCDROut.io.serDat From d4163a595a61b4b46a3911dd91926f2f54e43b58 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 22 Jul 2025 10:18:39 +0800 Subject: [PATCH 4/6] =?UTF-8?q?=E7=BA=A6=E6=9D=9F=E5=8F=82=E6=95=B0?= =?UTF-8?q?=E6=A3=80=E6=9F=A5?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/ShinTop.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 589023f..1cb23ca 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -81,6 +81,8 @@ abstract class ShinTopBase extends Module{ val up = Module(new CDRIn with CDRInMultiSample) down.multiCLK := multiCLK up.multiCLK := multiCLK + require( isMultiCLK == down.clkNum ) + require( isMultiCLK == up.clkNum ) (down, up) } From acf09cf11877164fac3e9b3a25afc7f03988922c Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 22 Jul 2025 11:24:47 +0800 Subject: [PATCH 5/6] =?UTF-8?q?=E5=BC=80=E5=A7=8B=E8=B0=83=E8=AF=95?= =?UTF-8?q?=EF=BC=8C=E6=95=B0=E6=8D=AE=E6=81=A2=E5=A4=8D=E4=B8=8D=E6=88=90?= =?UTF-8?q?=E5=8A=9F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/ShinTop.scala | 6 +- tb/shinTest/ShinTopSpiTb.v | 85 +++++++++++++++++++-- 2 files changed, 84 insertions(+), 7 deletions(-) diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 1cb23ca..4dd2d54 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -79,10 +79,12 @@ abstract class ShinTopBase extends Module{ val multiCLK = IO(Input(Vec(isMultiCLK, Bool()))) val down = Module(new CDRIn with CDRInMultiSample) val up = Module(new CDRIn with CDRInMultiSample) - down.multiCLK := multiCLK - up.multiCLK := multiCLK require( isMultiCLK == down.clkNum ) require( isMultiCLK == up.clkNum ) + + down.multiCLK := multiCLK + up.multiCLK := multiCLK + (down, up) } diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index adfb873..3cb022a 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -39,6 +39,8 @@ module ShinTopSpiTb( reg reset; reg clk8x; + reg [7:0] multiCLK; + wire [3:0] dDat_w; wire [3:0] uDat_w; @@ -66,11 +68,24 @@ module ShinTopSpiTb( wire [4:0] io_int_sig; +`define MULTICLK + ShinTop s_ShinTop_Mst( .clock(clock), .reset(reset | isSoftReset[0]), - .io_clk8x(clk8x), +`ifdef MULTICLK + .multiCLK_0(multiCLK[0]), + .multiCLK_1(multiCLK[1]), + .multiCLK_2(multiCLK[2]), + .multiCLK_3(multiCLK[3]), + .multiCLK_4(multiCLK[4]), + .multiCLK_5(multiCLK[5]), + .multiCLK_6(multiCLK[6]), + .multiCLK_7(multiCLK[7]), +`else + .clk8x(clk8x), +`endif .io_dDatIn(1'b0), .io_dDatOut(dDat_w[0]), .io_uDatIn(uDat_w[0]), @@ -104,7 +119,18 @@ ShinTop s_ShinTop_slv0( .clock(clock), .reset(reset | isSoftReset[1]), - .io_clk8x(clk8x), +`ifdef MULTICLK + .multiCLK_0(multiCLK[0]), + .multiCLK_1(multiCLK[1]), + .multiCLK_2(multiCLK[2]), + .multiCLK_3(multiCLK[3]), + .multiCLK_4(multiCLK[4]), + .multiCLK_5(multiCLK[5]), + .multiCLK_6(multiCLK[6]), + .multiCLK_7(multiCLK[7]), +`else + .clk8x(clk8x), +`endif .io_dDatIn(dDat_w[0]), .io_dDatOut(dDat_w[1]), .io_uDatIn(uDat_w[1]), @@ -137,7 +163,18 @@ ShinTop s_ShinTop_slv1( .clock(clock), .reset(reset | isSoftReset[2]), - .io_clk8x(clk8x), +`ifdef MULTICLK + .multiCLK_0(multiCLK[0]), + .multiCLK_1(multiCLK[1]), + .multiCLK_2(multiCLK[2]), + .multiCLK_3(multiCLK[3]), + .multiCLK_4(multiCLK[4]), + .multiCLK_5(multiCLK[5]), + .multiCLK_6(multiCLK[6]), + .multiCLK_7(multiCLK[7]), +`else + .clk8x(clk8x), +`endif .io_dDatIn(dDat_w[1]), .io_dDatOut(dDat_w[2]), .io_uDatIn(uDat_w[2]), @@ -170,7 +207,18 @@ ShinTop s_ShinTop_slv2( .clock(clock), .reset(reset | isSoftReset[3]), - .io_clk8x(clk8x), +`ifdef MULTICLK + .multiCLK_0(multiCLK[0]), + .multiCLK_1(multiCLK[1]), + .multiCLK_2(multiCLK[2]), + .multiCLK_3(multiCLK[3]), + .multiCLK_4(multiCLK[4]), + .multiCLK_5(multiCLK[5]), + .multiCLK_6(multiCLK[6]), + .multiCLK_7(multiCLK[7]), +`else + .clk8x(clk8x), +`endif .io_dDatIn(dDat_w[2]), .io_dDatOut(dDat_w[3]), .io_uDatIn(uDat_w[3]), @@ -203,7 +251,18 @@ ShinTop s_ShinTop_slv3( .clock(clock), .reset(reset | isSoftReset[4]), - .io_clk8x(clk8x), +`ifdef MULTICLK + .multiCLK_0(multiCLK[0]), + .multiCLK_1(multiCLK[1]), + .multiCLK_2(multiCLK[2]), + .multiCLK_3(multiCLK[3]), + .multiCLK_4(multiCLK[4]), + .multiCLK_5(multiCLK[5]), + .multiCLK_6(multiCLK[6]), + .multiCLK_7(multiCLK[7]), +`else + .clk8x(clk8x), +`endif .io_dDatIn(dDat_w[3]), .io_dDatOut(), .io_uDatIn(1'b0), @@ -274,6 +333,22 @@ initial begin forever begin #80 clock <= ~clock; end end + +generate + for( genvar i = 0; i < 8; i = i + 1 ) begin + initial begin + multiCLK[i] = 0; + for( integer j = i; j < 8; j = j + 1 ) begin + #20 + ; + end + forever begin #80 multiCLK[i] <= ~multiCLK[i]; end + end + end +endgenerate + + + initial begin spidata_file = $fopen("spi_trans_data.txt", "w"); From 9f88d26ba1c24740b0ff43d91272afa1cee83994 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 22 Jul 2025 11:49:33 +0800 Subject: [PATCH 6/6] =?UTF-8?q?=E5=A4=9A=E7=9B=B8=E4=BD=8D=E6=97=B6?= =?UTF-8?q?=E9=92=9F=E5=8F=AF=E4=BB=A5=E4=BD=BF=E7=94=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 27 ++++++++++++++++++----- tb/shinTest/ShinTopSpiTb.v | 2 +- 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 5d9b192..9648ff5 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -58,7 +58,7 @@ trait CDRInMultiSample{ this: CDRInBase => val clkNum: Int = 8 require(clkNum >= 4) - //multiCLK 需要按照超前相位接线，即0为最后到达，1次后 + //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先 val multiCLK = IO(Input(Vec(clkNum, Bool()))) // val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) } @@ -68,17 +68,31 @@ trait CDRInMultiSample{ this: CDRInBase => // val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) } // arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) ) - val arbCnt = RegInit("b1".U(clkNum.W)) - arbCnt := Cat( arbCnt(clkNum-2,0), arbCnt.extract(clkNum-1) ) // val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) } // when( sampleReg(0) ^ sampleReg(1) ){ // arbLock := arbCnt // } val arbLock = Reg(UInt( clkNum.W )) + + //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的 when( sampleReg(0) ^ sampleReg(1) ){ - arbLock := arbCnt - } + arbLock := "b1".U(clkNum.W) << 2 + } .elsewhen( sampleReg(1) ^ sampleReg(2) ){ + arbLock := "b1".U(clkNum.W) << 3 + } .elsewhen( sampleReg(2) ^ sampleReg(3) ){ + arbLock := "b1".U(clkNum.W) << 4 + } .elsewhen( sampleReg(3) ^ sampleReg(4) ){ + arbLock := "b1".U(clkNum.W) << 5 + } .elsewhen( sampleReg(4) ^ sampleReg(5) ){ + arbLock := "b1".U(clkNum.W) << 6 + } .elsewhen( sampleReg(5) ^ sampleReg(6) ){ + arbLock := "b1".U(clkNum.W) << 7 + } .elsewhen( sampleReg(6) ^ sampleReg(7) ){ + arbLock := "b1".U(clkNum.W) << 0 + } .elsewhen( sampleReg(7) ^ sampleReg(0) ){ + arbLock := "b1".U(clkNum.W) << 1 + } // val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext( @@ -94,7 +108,8 @@ trait CDRInMultiSample{ this: CDRInBase => Mux1H( (for { i <- 0 until clkNum; j <- 0 until clkNum } yield { //跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值 - ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((clkNum - 1 - i + j) % clkNum) + // ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((clkNum - 1 - i + j) % clkNum) + (arbLock === (1.U << i)) -> sampleReg(i) }) ) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 3cb022a..a9fb4a4 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -338,7 +338,7 @@ generate for( genvar i = 0; i < 8; i = i + 1 ) begin initial begin multiCLK[i] = 0; - for( integer j = i; j < 8; j = j + 1 ) begin + for( integer j = 0; j < i; j = j + 1 ) begin #20 ; end