写死16相位

Merge branch 'mp_eb_dev' into feature/multiPhaseCDRIn

# Conflicts:
#	src/main/scala/backBoard/ebus/CDRIn.scala
#	src/main/scala/backBoard/shin/ShinTop.scala
#	tb/shinTest/ShinTopSpiTb.v

src/main/scala/backBoard/shin/ShinTop.scala

@@ -5,20 +5,21 @@ import chisel3.util._
 
 
 class ShinTopIO extends Bundle{
-  val clk8x = Input(Bool())
 
   val dDatIn   = Input(Bool())
   val dDatOut  = Output(Bool())
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
+  val multiCLK = Input(Vec(16, Bool()))
+
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO
   val oqspi = new QSPIInterfaceIO
 
-  val rsp = Valid(new Bundle{
-    val isError = Bool()
-  })
+  // val rsp = Valid(new Bundle{
+  //   val isError = Bool()
+  // })
 
   val iSync = Output(Vec(4, Bool()))
   val oSync = Output(Vec(4, Bool()))
@@ -37,13 +38,20 @@ class ShinTopIO extends Bundle{
 
 
 abstract class ShinTopBase extends Module{
+
   val io: ShinTopIO = IO(new ShinTopIO)
 
 	val slaveParser  = Module(new SlaveParser )
 	val masterParser = Module(new MasterParser)
 
-  val downCDRIn  = Module(new CDRIn)
-  val upCDRIn    = Module(new CDRIn)
+  val downCDRIn = Module(new MPCDRIn)
+  val upCDRIn   = Module(new MPCDRIn)
+
+
+  downCDRIn.multiCLK := io.multiCLK
+  upCDRIn.multiCLK   := io.multiCLK
+
+
   val downCDROut = Module(new CDROut)
   val upCDROut   = Module(new CDROut)
 
@@ -61,12 +69,6 @@ abstract class ShinTopBase extends Module{
   io.isSoftReset := interface.io.isSoftReset
   io.interrupt   := interface.io.interrupt
 
-
-  downCDRIn.io.overCLK := io.clk8x
-  upCDRIn.io.overCLK := io.clk8x
-
-
-
   io.ospi  <> interface.io.ospi
   io.iqspi <> interface.io.iqspi
   io.oqspi <> interface.io.oqspi
@@ -288,7 +290,7 @@ trait ShinTopMaster{ this: ShinTopBase =>
   masterParser.io.req         := interface.io.txReq.valid
   // masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
 
-  io.rsp := masterParser.io.rsp
+  // io.rsp := masterParser.io.rsp
 
   masterParser.io.cReg := interface.io.cReg
   masterParser.io.mReg := interface.io.mReg