写死16相位
Merge branch 'mp_eb_dev' into feature/multiPhaseCDRIn # Conflicts: # src/main/scala/backBoard/ebus/CDRIn.scala # src/main/scala/backBoard/shin/ShinTop.scala # tb/shinTest/ShinTopSpiTb.v
This commit is contained in:
Ruige Lee
@@ -8,24 +8,29 @@ import chisel3.util._
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class CDRInIO extends Bundle{
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val axis = Decoupled(new AXIS_Bundle(8))
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val serDat = Input(Bool())
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val overCLK = Input(Bool())
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}
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abstract class CDRInBase extends Module{
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def sampleRate: Int = 4
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val io: CDRInIO = IO(new CDRInIO)
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val syncSerDat = Wire(Bool())
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}
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trait CDRInOverSample{ this: CDRInBase =>
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val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate+3 ) }
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val overCLK = IO(Input(Bool()))
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val sampleRate: Int = 4
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require(sampleRate >= 4)
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val sampleReg = withClockAndReset(overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate+3 ) }
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val flitReg = for( i <- 0 until sampleRate ) yield {
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withClockAndReset(io.overCLK.asClock, reset.asBool){
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withClockAndReset(overCLK.asClock, reset.asBool){
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RegNext(
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(sampleReg(i) & sampleReg(i+1)) |
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(sampleReg(i) & sampleReg(i+2)) |
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@@ -34,59 +39,19 @@ trait CDRInOverSample{ this: CDRInBase =>
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}
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}
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// val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
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// val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
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// val isArbLock = RegInit(false.B)
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// for( i <- 0 until sampleRate ){
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// arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) )
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// when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){
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// isArbLock := true.B
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// arbSel := i.U
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// }
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// }
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// when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){
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// isArbLock := false.B
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// }
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// val syncSerDat =
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// Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
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val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
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val arbCnt = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
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arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
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val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
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withClockAndReset(io.overCLK.asClock, reset.asBool){
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val arbLock = withClockAndReset(overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
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withClockAndReset(overCLK.asClock, reset.asBool){
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when( flitReg(0) ^ flitReg(1) ){
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arbLock := arbCnt
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}
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}
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val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext(
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val asyncSerDat = withClockAndReset(overCLK.asClock, reset.asBool){ RegNext(
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Mux1H(
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// Seq(
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// //(arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3),
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// (arbLock === (1.U << 0) & arbCnt === (1.U << 0)) -> sampleReg(3),
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// (arbLock === (1.U << 0) & arbCnt === (1.U << 1)) -> sampleReg(0),
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// (arbLock === (1.U << 0) & arbCnt === (1.U << 2)) -> sampleReg(1),
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// (arbLock === (1.U << 0) & arbCnt === (1.U << 3)) -> sampleReg(2),
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// (arbLock === (1.U << 1) & arbCnt === (1.U << 0)) -> sampleReg(2),
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// (arbLock === (1.U << 1) & arbCnt === (1.U << 1)) -> sampleReg(3),
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// (arbLock === (1.U << 1) & arbCnt === (1.U << 2)) -> sampleReg(0),
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// (arbLock === (1.U << 1) & arbCnt === (1.U << 3)) -> sampleReg(1),
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// (arbLock === (1.U << 2) & arbCnt === (1.U << 0)) -> sampleReg(1),
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// (arbLock === (1.U << 2) & arbCnt === (1.U << 1)) -> sampleReg(2),
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// (arbLock === (1.U << 2) & arbCnt === (1.U << 2)) -> sampleReg(3),
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// (arbLock === (1.U << 2) & arbCnt === (1.U << 3)) -> sampleReg(0),
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// (arbLock === (1.U << 3) & arbCnt === (1.U << 0)) -> sampleReg(0),
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// (arbLock === (1.U << 3) & arbCnt === (1.U << 1)) -> sampleReg(1),
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// (arbLock === (1.U << 3) & arbCnt === (1.U << 2)) -> sampleReg(2),
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// (arbLock === (1.U << 3) & arbCnt === (1.U << 3)) -> sampleReg(3),
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// )
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(for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield {
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//跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值
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((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> flitReg((sampleRate + 2 - i + j) % sampleRate)
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@@ -95,13 +60,88 @@ trait CDRInOverSample{ this: CDRInBase =>
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)}
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val syncSerDat = ShiftRegister( asyncSerDat, 2 )
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syncSerDat := ShiftRegister( asyncSerDat, 2 )
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}
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trait CDRInMultiSample{ this: CDRInBase =>
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val clkNum: Int = 16
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//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
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val multiCLK = IO(Input(Vec(16, Bool())))
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// val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
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val sampleReg = for( i <- 0 until 16 ) yield {
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withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
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}
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val flitReg = for( i <- 0 until 16 ) yield {
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if( i == 0 ) {
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(sampleReg(15) & sampleReg(0)) |
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(sampleReg(15) & sampleReg(1)) |
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(sampleReg(0) & sampleReg(1))
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} else if ( i > 0 && i < 15 ){
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(sampleReg(i-1) & sampleReg(i)) |
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(sampleReg(i-1) & sampleReg(i+1)) |
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(sampleReg(i) & sampleReg(i+1))
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} else// ( i == 15 )
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(sampleReg(14) & sampleReg(15)) |
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(sampleReg(14) & sampleReg(0)) |
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(sampleReg(15) & sampleReg(0))
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}
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val arbLock = Reg(UInt( 16.W ))
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//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
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when( flitReg(0) ^ flitReg(1) ){
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arbLock := "b1".U(16.W) << 2
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} .elsewhen( flitReg(1) ^ flitReg(2) ){
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arbLock := "b1".U(16.W) << 3
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} .elsewhen( flitReg(2) ^ flitReg(3) ){
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arbLock := "b1".U(16.W) << 4
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} .elsewhen( flitReg(3) ^ flitReg(4) ){
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arbLock := "b1".U(16.W) << 5
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} .elsewhen( flitReg(4) ^ flitReg(5) ){
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arbLock := "b1".U(16.W) << 6
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} .elsewhen( flitReg(5) ^ flitReg(6) ){
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arbLock := "b1".U(16.W) << 7
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} .elsewhen( flitReg(6) ^ flitReg(7) ){
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arbLock := "b1".U(16.W) << 8
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} .elsewhen( flitReg(7) ^ flitReg(8) ){
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arbLock := "b1".U(16.W) << 9
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} .elsewhen( flitReg(8) ^ flitReg(9) ){
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arbLock := "b1".U(16.W) << 10
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} .elsewhen( flitReg(9) ^ flitReg(10) ){
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arbLock := "b1".U(16.W) << 11
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} .elsewhen( flitReg(10) ^ flitReg(11) ){
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arbLock := "b1".U(16.W) << 12
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} .elsewhen( flitReg(11) ^ flitReg(12) ){
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arbLock := "b1".U(16.W) << 13
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} .elsewhen( flitReg(12) ^ flitReg(13) ){
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arbLock := "b1".U(16.W) << 14
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} .elsewhen( flitReg(13) ^ flitReg(14) ){
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arbLock := "b1".U(16.W) << 15
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} .elsewhen( flitReg(14) ^ flitReg(15) ){
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arbLock := "b1".U(16.W) << 0
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} .elsewhen( flitReg(15) ^ flitReg(0) ){
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arbLock := "b1".U(16.W) << 1
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}
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val asyncSerDat =
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Mux1H(
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(for { i <- 0 until clkNum } yield {
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(arbLock === (1.U << i)) -> flitReg(i)
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})
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)
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syncSerDat := ShiftRegister( asyncSerDat, 2 )
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}
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trait CDRInAxis{ this: CDRInBase =>
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@@ -120,7 +160,6 @@ trait CDRInAxis{ this: CDRInBase =>
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val bitCnt = Reg(UInt(4.W))
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val byteCnt = RegInit(0.U((12+1).W))
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val syncSerDat: Bool
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val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
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val shiftData = Dualb4b5Decoder(checkSFD(9,0))
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@@ -188,6 +227,10 @@ trait CDRInAxis{ this: CDRInBase =>
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}
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class CDRIn extends CDRInBase
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with CDRInAxis
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with CDRInOverSample
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class CDRIn extends CDRInBase with CDRInOverSample with CDRInAxis
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class MPCDRIn extends CDRInBase
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with CDRInAxis
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with CDRInMultiSample
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@@ -54,12 +54,17 @@ abstract class RoCC2CDRImplBase(outer: RoCC2CDR)(implicit p: Parameters) extends
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val cdrOutio = IO(Output(new RocCC2CDROutIO))
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val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
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when(true.B){
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print("Warning!!! New Code has not been reviewed!\n")
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}
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CDRIn(0).io.serDat := cdrInio.dDatIn
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CDRIn(1).io.serDat := cdrInio.uDatIn
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CDRIn(0).io.overCLK := cdrInio.overCLK
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CDRIn(1).io.overCLK := cdrInio.overCLK
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CDRIn(0).overCLK := cdrInio.overCLK
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CDRIn(1).overCLK := cdrInio.overCLK
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val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
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@@ -56,12 +56,15 @@ abstract class TL2CDRImplBase(outer: TL2CDR)(implicit p: Parameters) extends Laz
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val ( bus, edge ) = outer.node.in.head
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val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
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when(true.B){
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print("Warning!!! New Code has not been reviewed!\n")
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}
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CDRIn(0).io.serDat := io.dDatIn
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CDRIn(1).io.serDat := io.uDatIn
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CDRIn(0).io.overCLK := io.overCLK
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CDRIn(1).io.overCLK := io.overCLK
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CDRIn(0).overCLK := io.overCLK
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CDRIn(1).overCLK := io.overCLK
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val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
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@@ -5,20 +5,21 @@ import chisel3.util._
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class ShinTopIO extends Bundle{
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val clk8x = Input(Bool())
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val dDatIn = Input(Bool())
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val dDatOut = Output(Bool())
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val uDatIn = Input(Bool())
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val uDatOut = Output(Bool())
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val multiCLK = Input(Vec(16, Bool()))
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val iqspi = new QSPIInterfaceIO
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val ospi = new SSPIInterfaceIO
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val oqspi = new QSPIInterfaceIO
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val rsp = Valid(new Bundle{
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val isError = Bool()
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})
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// val rsp = Valid(new Bundle{
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// val isError = Bool()
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// })
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val iSync = Output(Vec(4, Bool()))
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val oSync = Output(Vec(4, Bool()))
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@@ -37,13 +38,20 @@ class ShinTopIO extends Bundle{
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abstract class ShinTopBase extends Module{
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val io: ShinTopIO = IO(new ShinTopIO)
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val slaveParser = Module(new SlaveParser )
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val masterParser = Module(new MasterParser)
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val downCDRIn = Module(new CDRIn)
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val upCDRIn = Module(new CDRIn)
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val downCDRIn = Module(new MPCDRIn)
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val upCDRIn = Module(new MPCDRIn)
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downCDRIn.multiCLK := io.multiCLK
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upCDRIn.multiCLK := io.multiCLK
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val downCDROut = Module(new CDROut)
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val upCDROut = Module(new CDROut)
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@@ -61,12 +69,6 @@ abstract class ShinTopBase extends Module{
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io.isSoftReset := interface.io.isSoftReset
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io.interrupt := interface.io.interrupt
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downCDRIn.io.overCLK := io.clk8x
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upCDRIn.io.overCLK := io.clk8x
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io.ospi <> interface.io.ospi
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io.iqspi <> interface.io.iqspi
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io.oqspi <> interface.io.oqspi
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@@ -288,7 +290,7 @@ trait ShinTopMaster{ this: ShinTopBase =>
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masterParser.io.req := interface.io.txReq.valid
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// masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
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io.rsp := masterParser.io.rsp
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// io.rsp := masterParser.io.rsp
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masterParser.io.cReg := interface.io.cReg
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masterParser.io.mReg := interface.io.mReg
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