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**抹除**加密特性

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This commit is contained in:
Ruige Lee
2025-07-30 15:36:18 +08:00
parent 1791a54dae
commit 8ba8ff0e9e
4 changed files with 5 additions and 34 deletions
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10
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -10,7 +10,6 @@ class CDRInIO extends Bundle{
val serDat = Input(Bool())
val overCLK = Input(Bool())
val initEncryptor = Flipped(Valid(UInt(128.W)))
}
@@ -19,9 +18,6 @@ abstract class CDRInBase extends Module{
val io: CDRInIO = IO(new CDRInIO)
val encryptor = Module(new Encryptor)
encryptor.io.init := io.initEncryptor
encryptor.io.op.ready := io.axis.fire
}
@@ -121,9 +117,9 @@ trait CDRInAxis{ this: CDRInBase =>
val payloadLen = RegInit(0.U(12.W))
when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
payloadLen := Cat( shiftData ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ), 0.U(4.W) )
payloadLen := Cat( shiftData, 0.U(4.W) )
} .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
payloadLen := Cat( payloadLen(11,4), shiftData(7,4) ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits(7,4), 0.U ) )
payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
}
stateNext :=
@@ -164,7 +160,7 @@ trait CDRInAxis{ this: CDRInBase =>
val axis_valid = RegInit(false.B)
val axis_tdata = RegEnable( shiftData ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tuser = false.B
val axis_tlast = RegNext( stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE, false.B )