diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index fae6248..021d7ba 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -10,7 +10,6 @@ class CDRInIO extends Bundle{
   val serDat = Input(Bool())
   val overCLK = Input(Bool())
 
-  val initEncryptor = Flipped(Valid(UInt(128.W)))
 }
 
 
@@ -19,9 +18,6 @@ abstract class CDRInBase extends Module{
 
   val io: CDRInIO = IO(new CDRInIO)
 
-  val encryptor = Module(new Encryptor)
-  encryptor.io.init := io.initEncryptor
-  encryptor.io.op.ready := io.axis.fire
 
 }
 
@@ -121,9 +117,9 @@ trait CDRInAxis{ this: CDRInBase =>
 
   val payloadLen = RegInit(0.U(12.W))
   when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
-    payloadLen := Cat( shiftData ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ), 0.U(4.W) )
+    payloadLen := Cat( shiftData, 0.U(4.W) )
   } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
-    payloadLen := Cat( payloadLen(11,4), shiftData(7,4) ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits(7,4), 0.U ) )
+    payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
   }
   
   stateNext := 
@@ -164,7 +160,7 @@ trait CDRInAxis{ this: CDRInBase =>
 
 
   val axis_valid = RegInit(false.B)
-  val axis_tdata = RegEnable( shiftData ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
+  val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
   val axis_tuser = false.B
   val axis_tlast = RegNext( stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE, false.B )
 
diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala
index 53ccdf0..4699a82 100644
--- a/src/main/scala/backBoard/ebus/CDROut.scala
+++ b/src/main/scala/backBoard/ebus/CDROut.scala
@@ -14,7 +14,6 @@ class CDROutIO extends Bundle{
   val axis = Flipped(Decoupled(new AXIS_Bundle(8))) 
   val serDat = Output(Bool())
 
-  val initEncryptor = Flipped(Valid(UInt(128.W)))
 
 }
 
@@ -22,9 +21,6 @@ class CDROutIO extends Bundle{
 class CDROut extends Module{
   val io: CDROutIO = IO(new CDROutIO)
 
-  val encryptor = Module(new Encryptor)
-  encryptor.io.init := io.initEncryptor
-  encryptor.io.op.ready := io.axis.fire
 
 
   def STATE_IDLE  = 0.U
@@ -72,10 +68,10 @@ class CDROut extends Module{
       when( stateCurr === STATE_PREAMBLE ){
         shiftData := MuxCase( ETH_PRE, Array(
           ( byteCnt === 6.U ) -> ETH_SFD,
-          ( byteCnt === 7.U ) -> Dualb4b5Encoder( io.axis.bits.tdata ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ) ),
+          ( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
         ))
       } .elsewhen( stateCurr === STATE_PAYLOAD ){
-        shiftData := Dualb4b5Encoder(io.axis.bits.tdata ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ) )
+        shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
       }
     }
   }
diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index bdbe97e..b6b1567 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -26,8 +26,6 @@ class CommonRegisterBundle extends Bundle{
 
   val spiSel    = UInt(2.W)
 
-  val encryptKey   = UInt(128.W)
-  val isEncrypt    = Bool()
 
   val intEnable = UInt(32.W)
   val intStatus = UInt(32.W)
@@ -172,7 +170,6 @@ class InterfaceIO extends Bundle{
 
   val sync = Output(Vec(4, Bool()))
 
-  val initEncryptor = Valid(UInt(128.W))
 
   val isSoftReset = Output(Bool())
   val intMstTrig  = Input(Vec(2, Bool()))
@@ -255,12 +252,8 @@ abstract class InterfaceBase extends Module{
 
 
 
-      ((0 until 16).map{ i =>
-        (addr === ("h50".U(16.W) + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
-      }) ++
 
       Seq(
-        (addr === "h60".U ) -> cReg.isEncrypt,
         (addr === "h70".U ) -> cReg.intEnable(7,0),
         (addr === "h71".U ) -> cReg.intEnable(15,8),
         (addr === "h72".U ) -> cReg.intEnable(23,16),
@@ -497,14 +490,6 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   cReg.busRate := RegEnable( dataw, "h55".U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
   cReg.spiSel  := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
 
-  cReg.encryptKey :=
-    Cat(
-      (0 until 16).map{ i =>
-        RegEnable( dataw, 0.U, isEnW & addrw === ("h50".U(16.W) + i.U) & cReg.mstOrSlv === 0.U )
-      }.reverse
-    )
-
-  cReg.isEncrypt := RegEnable( dataw.extract(0), 0.U, isEnW & addrw === "h60".U & cReg.mstOrSlv === 0.U )
 
   mReg.txSM     := RegEnable( dataw(2,1), 0.U, isEnW & addrw === "h20".U )
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U, isEnW & addrw === "h20".U )
@@ -985,8 +970,6 @@ with InterfaceSystem
   sReg.isDevOnRightModify := io.isDevOnRightModify
   sReg.indexOfRightDev    := io.indexOfRightDev
 
-  io.initEncryptor.valid := dataw.extract(0) & isEnW & addrw === "h60".U & cReg.mstOrSlv === 0.U //cReg.isEncrypt
-  io.initEncryptor.bits  := cReg.encryptKey
 
 
 }
\ No newline at end of file
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 9f210f0..5753749 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -80,17 +80,13 @@ abstract class ShinTopBase extends Module{
 
   downCDRIn.io.serDat  := io.dDatIn
   downCDRIn.io.overCLK := io.clk8x
-  downCDRIn.io.initEncryptor := interface.io.initEncryptor
 
   upCDRIn.io.serDat  := io.uDatIn
   upCDRIn.io.overCLK := io.clk8x
-  upCDRIn.io.initEncryptor := interface.io.initEncryptor
 
   io.dDatOut := downCDROut.io.serDat
   io.uDatOut := upCDROut.io.serDat
 
-  downCDROut.io.initEncryptor := interface.io.initEncryptor
-  upCDROut.io.initEncryptor   := interface.io.initEncryptor
 
   //override
   when( slaveParser.io.isLoop & interface.io.cReg.modeSel === false.B){