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中断节点化

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This commit is contained in:
RuigeLee
2023-07-11 22:02:41 +08:00
parent 2d720b7c8d
commit 8b2121959e
2 changed files with 37 additions and 17 deletions
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19
src/main/scala/mac/MAC.scala
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@@ -6,6 +6,7 @@ import chisel3.util._
import org.chipsalliance.cde.config._ import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
@@ -32,10 +33,17 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
// DTS
val dtsdevice = new SimpleDevice("mac",Seq("mac_0"))
val int_node = IntSourceNode(IntSourcePortSimple(num = 1, resources = dtsdevice.int))
lazy val module = new MacImp(this) lazy val module = new MacImp(this)
} }
@@ -58,7 +66,7 @@ class MacIO extends Bundle with MDIO{
val mcoll_pad_i = Input(Bool()) val mcoll_pad_i = Input(Bool())
val mcrs_pad_i = Input(Bool()) val mcrs_pad_i = Input(Bool())
val int_o = Output(Bool()) // val int_o = Output(Bool())
} }
class MacImp(outer: Mac)(implicit p: Parameters) extends LazyModuleImp(outer) with HasMacParameters{ class MacImp(outer: Mac)(implicit p: Parameters) extends LazyModuleImp(outer) with HasMacParameters{
@@ -68,6 +76,7 @@ class MacImp(outer: Mac)(implicit p: Parameters) extends LazyModuleImp(outer) wi
val ( slv_bus, slv_edge ) = outer.tlMasterNode.in.head val ( slv_bus, slv_edge ) = outer.tlMasterNode.in.head
val ( mst_bus, mst_edge ) = outer.tlClientNode.out.head val ( mst_bus, mst_edge ) = outer.tlClientNode.out.head
val (int, _) = outer.int_node.out(0)
@@ -377,7 +386,8 @@ r_FIAD := ethReg.io.r_FIAD
r_CtrlData := ethReg.io.r_CtrlData r_CtrlData := ethReg.io.r_CtrlData
r_MAC := ethReg.io.r_MAC r_MAC := ethReg.io.r_MAC
r_TxBDNum := ethReg.io.r_TxBDNum r_TxBDNum := ethReg.io.r_TxBDNum
io.int_o := ethReg.io.int_o // io.int_o := ethReg.io.int_o
int(0) := ethReg.io.int_o
r_TxPauseTV := ethReg.io.r_TxPauseTV r_TxPauseTV := ethReg.io.r_TxPauseTV
r_TxPauseRq := ethReg.io.r_TxPauseRq r_TxPauseRq := ethReg.io.r_TxPauseRq
@@ -813,3 +823,8 @@ val rxethmac = Module(new MacRx)
} }

35
src/test/scala/gcd/Mac_test_top.scala
View File

@@ -6,13 +6,13 @@ import chisel3.util._
import org.chipsalliance.cde.config._ import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
class MacTest(implicit p: Parameters) extends Mac{
class MacTest(implicit p: Parameters) extends LazyModule with HasMacParameters{
val mac = LazyModule( new Mac )
val tlRAM = TLRAM( val tlRAM = TLRAM(
@@ -25,27 +25,32 @@ class MacTest(implicit p: Parameters) extends LazyModule with HasMacParameters{
devName = None, devName = None,
) )
tlRAM := mac.tlClientNode tlRAM := tlClientNode
val tlClientIONode = val tlClientIONode =
TLClientNode(Seq(TLMasterPortParameters.v1( TLClientNode(Seq(TLMasterPortParameters.v1(
Seq(TLMasterParameters.v1( Seq(TLMasterParameters.v1(
name = "tlSlvIO", name = "tlSlvIO",
sourceId = IdRange(0, 1), sourceId = IdRange(0, 1),
)) ))
))) )))
mac.tlMasterNode := tlClientIONode tlMasterNode := tlClientIONode
val intSinkNode = IntSinkNode(IntSinkPortSimple())
intSinkNode := int_node
val tlSlv = InModuleBody { val tlSlv = InModuleBody {
tlClientIONode.makeIOs() tlClientIONode.makeIOs()
} }
lazy val module = new LazyModuleImp(this) { val int = InModuleBody {
val io = IO(new MacIO with MDIO) intSinkNode.makeIOs()
io <> mac.module.io
} }
} }