From 8b2121959e3afd8d6a76fe5b021a3617d5636b76 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Tue, 11 Jul 2023 22:02:41 +0800
Subject: [PATCH] =?UTF-8?q?=E4=B8=AD=E6=96=AD=E8=8A=82=E7=82=B9=E5=8C=96?=
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---
 src/main/scala/mac/MAC.scala          | 19 +++++++++++++--
 src/test/scala/gcd/Mac_test_top.scala | 35 +++++++++++++++------------
 2 files changed, 37 insertions(+), 17 deletions(-)

diff --git a/src/main/scala/mac/MAC.scala b/src/main/scala/mac/MAC.scala
index 48e7edd..9af1111 100644
--- a/src/main/scala/mac/MAC.scala
+++ b/src/main/scala/mac/MAC.scala
@@ -6,6 +6,7 @@ import chisel3.util._
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
 
 class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
 
@@ -32,10 +33,17 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
 
 
 
+  // DTS
+  val dtsdevice = new SimpleDevice("mac",Seq("mac_0"))
+
+  val int_node = IntSourceNode(IntSourcePortSimple(num = 1, resources = dtsdevice.int))
+
+
   lazy val module = new MacImp(this)
 
 
 
+
 }
 
 
@@ -58,7 +66,7 @@ class MacIO extends Bundle with MDIO{
   val mcoll_pad_i = Input(Bool())
   val mcrs_pad_i  = Input(Bool())
 
-  val int_o = Output(Bool())
+  // val int_o = Output(Bool())
 }
 
 class MacImp(outer: Mac)(implicit p: Parameters) extends LazyModuleImp(outer) with HasMacParameters{
@@ -68,6 +76,7 @@ class MacImp(outer: Mac)(implicit p: Parameters) extends LazyModuleImp(outer) wi
   val ( slv_bus, slv_edge ) = outer.tlMasterNode.in.head
   val ( mst_bus, mst_edge ) = outer.tlClientNode.out.head
   
+  val (int, _) = outer.int_node.out(0)
 
 
 
@@ -377,7 +386,8 @@ r_FIAD      := ethReg.io.r_FIAD
 r_CtrlData  := ethReg.io.r_CtrlData
 r_MAC       := ethReg.io.r_MAC
 r_TxBDNum   := ethReg.io.r_TxBDNum
-io.int_o    := ethReg.io.int_o
+// io.int_o    := ethReg.io.int_o
+  int(0)   := ethReg.io.int_o
 r_TxPauseTV := ethReg.io.r_TxPauseTV
 r_TxPauseRq := ethReg.io.r_TxPauseRq
 
@@ -813,3 +823,8 @@ val rxethmac = Module(new MacRx)
 
 
 }
+
+
+
+
+
diff --git a/src/test/scala/gcd/Mac_test_top.scala b/src/test/scala/gcd/Mac_test_top.scala
index aec2aec..ee7b826 100644
--- a/src/test/scala/gcd/Mac_test_top.scala
+++ b/src/test/scala/gcd/Mac_test_top.scala
@@ -6,13 +6,13 @@ import chisel3.util._
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
 
 
 
+class MacTest(implicit p: Parameters) extends Mac{
 
-class MacTest(implicit p: Parameters) extends LazyModule with HasMacParameters{
 
-	val mac = LazyModule( new Mac )
 
 
 	val tlRAM = TLRAM(
@@ -25,27 +25,32 @@ class MacTest(implicit p: Parameters) extends LazyModule with HasMacParameters{
     devName = None,
   )
 
-	tlRAM := mac.tlClientNode
+	tlRAM := tlClientNode
 
 
 
-		val tlClientIONode = 
-			TLClientNode(Seq(TLMasterPortParameters.v1(
-				Seq(TLMasterParameters.v1(
-					name = "tlSlvIO",
-					sourceId = IdRange(0, 1),
-				))
-			)))
+	val tlClientIONode = 
+		TLClientNode(Seq(TLMasterPortParameters.v1(
+			Seq(TLMasterParameters.v1(
+				name = "tlSlvIO",
+				sourceId = IdRange(0, 1),
+			))
+		)))
 
-		mac.tlMasterNode := tlClientIONode
+	tlMasterNode := tlClientIONode
+
+
+	val intSinkNode = IntSinkNode(IntSinkPortSimple())
+	intSinkNode := int_node
 
     val tlSlv = InModuleBody {
       tlClientIONode.makeIOs()
     }
 
-	lazy val module = new LazyModuleImp(this) {
-		val io = IO(new MacIO with MDIO)
-
-		io <> mac.module.io
+	val int = InModuleBody {
+	  intSinkNode.makeIOs()
 	}
+
+
+
 }
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