将vcs仿真流程修正得更好

This commit is contained in:
2025-09-07 00:10:41 +08:00
parent 4a21e4b2ba
commit 8a7e4981fb
5 changed files with 45 additions and 12 deletions

View File

@@ -407,7 +407,8 @@ initial begin
$display("Time Out !!!");
$fclose(spidata_file);
$stop;
//$stop;
$finish;
end
initial begin
@@ -438,8 +439,16 @@ initial
begin
spidata_file = $fopen("spi_trans_data.txt", "w");
if (!spidata_file) $display("文件打开失败");
$dumpfile("./generated/wave.fst"); //生成的vcd文件名称
`ifdef VCS_COMPILE
$dumpfile("./generated/wave.vcd"); //生成的vcd文件名称
$dumpvars(0, ShinTopSpiTb);//tb模块名称
`endif
`ifdef IVERILOG_COMPILE
$dumpfile("./generated/wave.fst"); //生成的fst文件名称
$dumpvars(0, ShinTopSpiTb);//tb模块名称
`endif
end
always @(posedge reset) begin
@@ -1092,7 +1101,8 @@ initial begin
#1000000
$display("Testcase Finished! Time Out !!!");
$fclose(spidata_file);
$stop;
//$stop;
$finish;
end