将vcs仿真流程修正得更好

tb/shinTest/Makefile_vcs

@@ -2,11 +2,12 @@
 
 OUTPUT = shin_test
 
-VCS = vcs -sverilog +v2k -timescale=1ns/1ps                             \
-	-debug_all                                                    \
-	-full64                                                       \
-	-o ${OUTPUT}                                                  \
-	-l compile.log                                                \
+VCS = vcs -sverilog +v2k -timescale=1ns/1ps   \
+	-full64                                   \
+	-o ${OUTPUT}                              \
+	-l compile.log                            \
+	-debug_access+none						  \
+	+define+VCS_COMPILE						  \
 
 SIM = ./${OUTPUT} -l run.log
 
@@ -16,6 +17,16 @@ testShin_vcs:
 	rm -rf generated/log/*
 	${VCS} -f ./shinTest_vcs.f
 	${SIM}
+	python3 ./shinTest/check_testcase.py
+
+testShinClk_vcs:
+	python3 ./shinTest/gen_pkt_clk.py
+	mkdir -p generated/log
+	rm -rf generated/log/*
+	${VCS} -f ./shinTestClk_vcs.f
+	${SIM}
+	python3 ./shinTest/check_testcase.py
+
 sim:
 	${SIM}