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将vcs仿真流程修正得更好

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bacon
2025-09-07 00:10:41 +08:00
parent 4a21e4b2ba
commit 8a7e4981fb
5 changed files with 45 additions and 12 deletions
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3
Makefile
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@@ -49,6 +49,7 @@ testShin:
-y ./generated/shin \
-I ./generated/shin \
-D RANDOMIZE_REG_INIT \
-D IVERILOG_COMPILE \
./tb/shinTest/ShinTopSpiTb.v
vvp -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
./tb/shinTest/check_testcase.py
@@ -62,6 +63,7 @@ testShinClk:
-y ./generated/shin \
-I ./generated/shin \
-D RANDOMIZE_REG_INIT \
-D IVERILOG_COMPILE \
./tb/shinTest/ShinTopSpiTb_clk.v
vvp -N ./tb/build/shinTest_clk.iverilog -lxt2 -fst || true
./tb/shinTest/check_testcase.py
@@ -74,6 +76,7 @@ testCDR:
-I ./generated/SimCDR \
-I ./generated/shin \
-D RANDOMIZE_REG_INIT \
-D IVERILOG_COMPILE \
./tb/shinTest/SimCDRTb.v
vvp -N ./tb/build/simCDR.iverilog -lxt2 -fst