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RuigeLee
2024-10-17 18:32:11 +08:00
parent 7e99cf4489
commit 8950af8a47
2 changed files with 18 additions and 16 deletions
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32
src/main/scala/backBoard/shin/ShinSlv.scala
View File

@@ -241,6 +241,8 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
val upOldHead = Reg( new Header_Info_Bundle )
val upNewHead = Reg( new Header_Info_Bundle )
val upPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) )
upStreamCdrIn.io.axis <> upPendBuf.io.enq
val upRecvStateNext = Wire( UInt(3.W) )
val upRecvStateCurr = RegNext( upRecvStateNext, 0.U )
@@ -250,15 +252,15 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
val isLastDevice: Bool
upRecvStateNext := Mux1H(Seq(
(upRecvStateCurr === UpRecvStateIdle ) -> Mux( upStreamCdrIn.io.axis.valid, UpRecvStateOHead, UpRecvStateIdle ),
(upRecvStateCurr === UpRecvStateOHead) -> Mux( upStreamCdrIn.io.axis.fire, Mux( ~upStreamCdrIn.io.axis.bits.tlast, Mux( upRecvCnt === ((headByte)-1).U, UpRecvStateFData, UpRecvStateOHead), UpRecvStateIdle), UpRecvStateOHead ),
(upRecvStateCurr === UpRecvStateFData) -> Mux( upStreamCdrIn.io.axis.fire, Mux( ~upStreamCdrIn.io.axis.bits.tlast, Mux( upRecvCnt === (upOldHead.length - 1.U), UpRecvStateCRC, UpRecvStateFData), UpRecvStateIdle), UpRecvStateFData ),
(upRecvStateCurr === UpRecvStateCRC ) -> Mux( upStreamCdrIn.io.axis.fire & upStreamCdrIn.io.axis.bits.tlast, UpRecvStateIdle, UpRecvStateCRC ),
(upRecvStateCurr === UpRecvStateIdle ) -> Mux( upPendBuf.io.deq.valid, UpRecvStateOHead, UpRecvStateIdle ),
(upRecvStateCurr === UpRecvStateOHead) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( upRecvCnt === ((headByte)-1).U, UpRecvStateFData, UpRecvStateOHead), UpRecvStateIdle), UpRecvStateOHead ),
(upRecvStateCurr === UpRecvStateFData) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( upRecvCnt === (upOldHead.length - 1.U), UpRecvStateCRC, UpRecvStateFData), UpRecvStateIdle), UpRecvStateFData ),
(upRecvStateCurr === UpRecvStateCRC ) -> Mux( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast, UpRecvStateIdle, UpRecvStateCRC ),
))
when( upRecvStateCurr =/= upRecvStateNext){
upRecvCnt := 0.U
} .elsewhen( upStreamCdrIn.io.axis.fire ){
} .elsewhen( upPendBuf.io.deq.fire ){
upRecvCnt := upRecvCnt + 1.U
}
@@ -269,8 +271,8 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
//---------------
when( (upRecvStateCurr === UpRecvStateOHead & upStreamCdrIn.io.axis.fire) ){
upOldHead := Cat( upOldHead.asUInt.tail(8), upStreamCdrIn.io.axis.bits.tdata ).asTypeOf(new Header_Info_Bundle)
when( (upRecvStateCurr === UpRecvStateOHead & upPendBuf.io.deq.fire) ){
upOldHead := Cat( upOldHead.asUInt.tail(8), upPendBuf.io.deq.bits.tdata ).asTypeOf(new Header_Info_Bundle)
} .elsewhen( isLastDownStreamEnd ){
upOldHead.operator := downOldHead.operator
upOldHead.length := 0.U
@@ -295,7 +297,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
val isUpNewHeadCreated =
RegNext(upRecvStateCurr === UpRecvStateOHead & upRecvStateNext === UpRecvStateFData, false.B) | //补一拍
isLastDownStreamEnd
RegNext(isLastDownStreamEnd, false.B)
when( isUpNewHeadCreated ){
upNewHead.length := upOldHead.length + upLocalDataByte
@@ -303,19 +305,19 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
upNewHead.param := upOldHead.param
}
val upForwardDataByte = upNewHead.length
val upForwardDataByte = upOldHead.length
//---------------
upStreamFifo.io.enq.valid :=
upRecvStateCurr === UpRecvStateFData & upStreamCdrIn.io.axis.fire
upStreamFifo.io.enq.bits.tdata := upStreamCdrIn.io.axis.bits.tdata
upStreamFifo.io.enq.bits.tuser := upStreamCdrIn.io.axis.bits.tuser
upStreamFifo.io.enq.bits.tlast := upRecvCnt === (upForwardDataByte -1.U) | upStreamCdrIn.io.axis.bits.tlast
upRecvStateCurr === UpRecvStateFData & upPendBuf.io.deq.fire
upStreamFifo.io.enq.bits.tdata := upPendBuf.io.deq.bits.tdata
upStreamFifo.io.enq.bits.tuser := upPendBuf.io.deq.bits.tuser
upStreamFifo.io.enq.bits.tlast := upRecvCnt === (upForwardDataByte -1.U) | upPendBuf.io.deq.bits.tlast
upStreamCdrIn.io.axis.ready :=
upPendBuf.io.deq.ready :=
(upRecvStateCurr === UpRecvStateOHead) |
((upRecvStateCurr === UpRecvStateFData) & upStreamFifo.io.enq.ready) |
(upRecvStateCurr === UpRecvStateCRC )
@@ -338,7 +340,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
} .elsewhen( upRecvStateCurr === UpRecvStateFData & upRecvStateNext === UpRecvStateIdle ){
isUpStreamError := true.B
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
} .elsewhen( upRecvStateCurr === UpRecvStateCRC & (upRecvCnt > 3.U | (upStreamCdrIn.io.axis.fire & upStreamCdrIn.io.axis.bits.tlast & upRecvCnt < 3.U)) ){
} .elsewhen( upRecvStateCurr === UpRecvStateCRC & (upRecvCnt > 3.U | (upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & upRecvCnt < 3.U)) ){
isUpStreamError := true.B
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
}

2
tb/ShinBack_tb.v
View File

@@ -92,7 +92,7 @@ module ShinBack_tb();
.clock(clock),
.reset(reset),
.io_isOnline(),
.io_isLast(1'b0),
.io_isLast(1'b1),
.io_DCIn(1'b0),
.io_downSer_out(),
.io_downSer_in(downStreamDat[3]),