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backplaneslv compile pass

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Signed-off-by: Ruige <295054118@whut.edu.cn>
This commit is contained in:
Ruige
2023-07-25 21:05:43 +08:00
parent b1fd2db2e0
commit 85fe9175e6
6 changed files with 238 additions and 119 deletions
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25
src/test/scala/gcd/test.scala
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@@ -1,6 +1,8 @@
package test
import MAC._
import BACK._
import chisel3._
import chisel3.stage._
import freechips.rocketchip.diplomacy._
@@ -10,19 +12,20 @@ import org.chipsalliance.cde.config._
object testModule extends App {
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => {
// new Mac
// })
// ))
val cfg = new MacCfg
(new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => {
val soc = LazyModule(new MacTest()(cfg))
soc.module
new BackBoardSlv
})
))
))
// val cfg = new MacCfg
// (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(
// ChiselGeneratorAnnotation(() => {
// val soc = LazyModule(new MacTest()(cfg))
// soc.module
// })
// ))
}