diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala
new file mode 100644
index 0000000..cf3deb1
--- /dev/null
+++ b/src/main/scala/backBoard/BackBoardSlv.scala
@@ -0,0 +1,105 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class BackBoardSlvIO extends Bundle{
+  val localHost = Input(UInt(6.W))
+
+  val upStreamReqDat    = Input( Bool() )
+  val downStreamReqDat  = Input( Bool() )
+
+  val upStreamRespdat   = Output(Bool())
+  val downStreamRespdat = Output(Bool())
+
+  val refClk            = Input( Vec(4, Bool()) )
+}
+
+
+abstract class BackBoardSlvBase extends Module{
+  val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
+
+
+  val upStreamReq    = Module(new CDR4InBus)
+  val downStreamReq  = Module(new CDR4InBus)
+
+  val upStreamResp   = Module(new CDROutBus)
+  val downStreamResp = Module(new CDROutBus)
+
+  upStreamReq.io.refClk   := io.refClk
+  downStreamReq.io.refClk := io.refClk
+  upStreamReq.io.dat      := io.upStreamReqDat
+  downStreamReq.io.dat    := io.downStreamReqDat
+
+  io.upStreamRespdat   := upStreamResp.io.dat
+  io.downStreamRespdat := downStreamResp.io.dat
+
+
+
+  def IDLE            = 0.U
+  def UPSTREAM_RESP   = 1.U
+  def DOWNSTREAM_RESP = 2.U
+
+  val stateNext = Wire( UInt(2.W) )
+  val stateCurr = RegNext(stateNext, 0.U)
+
+  stateNext := Mux1H(Seq(
+    (stateCurr === IDLE)            -> Mux(upStreamReq.io.latDat.fire, Mux(upStreamReq.io.latDat.bits.address(5,1) === io.localHost, UPSTREAM_RESP, DOWNSTREAM_RESP), Mux(downStreamReq.io.latDat.fire, UPSTREAM_RESP, IDLE) ),
+    (stateCurr === UPSTREAM_RESP)   -> Mux(upStreamResp.io.pkgDat.fire,   IDLE, UPSTREAM_RESP ),
+    (stateCurr === DOWNSTREAM_RESP) -> Mux(downStreamResp.io.pkgDat.fire, IDLE, DOWNSTREAM_RESP ),
+  ))
+
+  val upStreamReqReady    = RegInit(false.B); upStreamReq.io.latDat.ready   := upStreamReqReady
+  val downStreamReqReady  = RegInit(false.B); downStreamReq.io.latDat.ready := downStreamReqReady
+
+  val upStreamRespValid   = RegInit(false.B); upStreamResp.io.pkgDat.valid := upStreamRespValid
+  val upStreamRespInfo    = Reg(new CDRData); upStreamResp.io.pkgDat.bits  := upStreamRespInfo
+  val downStreamRespValid = RegInit(false.B); downStreamResp.io.pkgDat.valid := downStreamRespValid
+  val downStreamRespInfo  = Reg(new CDRData); downStreamResp.io.pkgDat.bits  := downStreamRespInfo
+
+  val registersRD = Wire(UInt(32.W))
+
+
+
+}
+
+trait StatusControl{ this: BackBoardSlvBase =>
+
+  when( upStreamResp.io.pkgDat.fire ){
+    upStreamRespValid := false.B
+  } .elsewhen( downStreamResp.io.pkgDat.fire ){
+    downStreamRespValid := false.B
+  }.elsewhen( upStreamReq.io.latDat.fire ){
+    upStreamReqReady := false.B
+
+    when( upStreamReq.io.latDat.bits.address(5,1) === io.localHost ){
+      upStreamRespValid := true.B
+      upStreamRespInfo.address  := upStreamReq.io.latDat.bits.address
+      upStreamRespInfo.register := upStreamReq.io.latDat.bits.register
+      upStreamRespInfo.data     := Mux(upStreamReq.io.latDat.bits.address.extract(0) === 0.U, registersRD, 0.U ) 
+      upStreamRespInfo.hash     := 0.U
+
+    } .otherwise{
+      downStreamRespValid := true.B
+      downStreamRespInfo  := upStreamReq.io.latDat.bits
+    }
+
+  } .elsewhen( downStreamReq.io.latDat.fire ){
+    downStreamReqReady := false.B
+
+    upStreamRespValid := true.B
+    upStreamRespInfo  := downStreamReq.io.latDat.bits
+  } .elsewhen( downStreamReq.io.latDat.valid & ~downStreamReq.io.latDat.ready && stateCurr === IDLE ){
+    downStreamReqReady := true.B
+  } .elsewhen( upStreamReq.io.latDat.valid & ~upStreamReq.io.latDat.ready & ~downStreamReq.io.latDat.valid & stateCurr === IDLE ){
+    upStreamReqReady := true.B
+  }
+
+
+
+}
+
+
+class BackBoardSlv extends BackBoardSlvBase with LocalRegisters
+
diff --git a/src/main/scala/backBoard/CDRBus.scala b/src/main/scala/backBoard/CDR4InBus.scala
similarity index 52%
rename from src/main/scala/backBoard/CDRBus.scala
rename to src/main/scala/backBoard/CDR4InBus.scala
index a5a2759..05af814 100644
--- a/src/main/scala/backBoard/CDRBus.scala
+++ b/src/main/scala/backBoard/CDR4InBus.scala
@@ -1,14 +1,18 @@
-package MAC
+package BACK
 
 import chisel3._
 import chisel3.util._
 
+import freechips.rocketchip.util._
+
+
 class CDRData extends Bundle{
   val address  = UInt(6.W)
   val register = UInt(8.W)
   val data     = UInt(32.W)
-  val hash     = UInt(2.W)
+  val hash     = UInt(16.W)
 
+  def crcHash = 0.U
   def isHashPass = true.B
 
 }
@@ -18,7 +22,7 @@ class CDRInBusIO() extends Bundle{
   val dat = Input(Bool())
 
 
-  val latchDat = Decoupled(new CDRData)
+  val latDat = Decoupled(new CDRData)
   val flush = Input(Bool())
 }
 
@@ -27,30 +31,30 @@ class CDRInBusIO() extends Bundle{
 class CDRInBus() extends Module{
   val io: CDRInBusIO = IO(new CDRInBusIO())
 
-  val latchValid = RegInit(false.B)
-  val latchInfo = RegInit(0.U.asTypeof(new CDRData))
+  val latValid = RegInit(false.B)
+  val latInfo = RegInit(0.U.asTypeOf(new CDRData))
   val shiftDat = RegInit(0.U((1+2+ ((new CDRData).getWidth) ).W))
-  val transInfo = shiftDat(1+2+((new CDRData).getWidth)-2,2).asTypeof(new CDRData)
+  val transInfo = shiftDat(1+2+((new CDRData).getWidth)-2,2).asTypeOf(new CDRData)
 
   val isHashPass = transInfo.isHashPass
 
 
-  when( flush ){
+  when( io.flush ){
     shiftDat   := 0.U
-    latchValid := false.B
+    latValid := false.B
   } .elsewhen( shiftDat.extract(1+2+((new CDRData).getWidth)-1) =/= 1.U ){
     shiftDat := Cat(shiftDat << 1 , io.dat)
   } .elsewhen( shiftDat.extract(1+2+((new CDRData).getWidth)-1) === 1.U ){
-    when( passHash ){
-      latchValid := true.B
-      latchInfo  := transInfo
+    when( transInfo.isHashPass ){
+      latValid := true.B
+      latInfo  := transInfo
     } .otherwise{
       shiftDat   := 0.U
     }
   }
 
-  io.latachDat.valid := latchValid
-  io.latachDat.bits  := latchInfo
+  io.latDat.valid := latValid
+  io.latDat.bits  := latInfo
 
 }
 
@@ -64,42 +68,42 @@ class CDRInBus() extends Module{
 
 
 class CDR4InBusIO extends Bundle{
-  val dat    = Input( Vec(4, Bool()) )
+  val dat    = Input( Bool() )
   val refClk = Input( Vec(4, Bool()) )
 
-  val syncDat = Decoupled(new CDRData)
+  val latDat = Decoupled(new CDRData)
 }
 
 class CDR4InBus extends Module{
   val io: CDR4InBusIO = IO(new CDR4InBusIO)
 
-  val inBusAsync = ( 0 until 4 ).map{
-    Module(new CDRInBus)
-  }
+  val inBusAsync = ( 0 until 4 ).map{ i => Module(new CDRInBus) }
 
 
-  val inBusToAsync = Wire( Vec(4, new AsyncBundle(new CDRInBus)) )
-  val inBusSyncIO = Vec(4, Decoupled(new CDRData) )
+  val inBusToAsync = for( i <- 0 until 4 ) yield { Wire( new AsyncBundle(new CDRData) ) }
+  val inBusSyncIO = for( i <- 0 until 4 ) yield {  Wire (new DecoupledIO(new CDRData) ) }
 
   val inBusMuxValid = RegInit(false.B)
-  val inBusMuxInfo  = RegInit(0.U.asTypeof(new CDRData))
+  val inBusMuxInfo  = RegInit(0.U.asTypeOf(new CDRData))
 
-  io.syncDat.valid := inBusMuxValid
-  io.syncDat.bits  := inBusMuxInfo
+  io.latDat.valid := inBusMuxValid
+  io.latDat.bits  := inBusMuxInfo
 
   for( i <- 0 until 4 ){
-    inBusAsync(i).clock    := io.refClk(i).clock
-    inBusAsync(i).io.dat   := io.dat(i)
-    inBusAsync(i).io.flush := io.syncDat.fire
+    inBusAsync(i).clock    := io.refClk(i).asClock
+    inBusAsync(i).io.dat   := io.dat
+    inBusAsync(i).io.flush := io.latDat.fire
 
-    inBusToAsync(i) <> ToAsyncBundle( inBusSyncIO(i), AsyncQueueParams(sync=2) )
-      
-    withClockAndReset( io.refClk(i).clock, reset ) {
-      inBusAsync(i).io.syncDat <> FromAsyncBundle( inBusToAsync, 2 )      
-    }   
+    // inBusToAsync(i) <> ToAsyncBundle( , AsyncQueueParams(sync=2) )
+    inBusSyncIO(i) <> FromAsyncBundle( inBusToAsync(i), 2 )
+
+    withClockAndReset( io.refClk(i).asClock, reset ) {
+      inBusToAsync(i) <> ToAsyncBundle( inBusAsync(i).io.latDat, AsyncQueueParams(sync=2) )
+    }
+    inBusSyncIO(i).ready := false.B
   }
 
-  when( io.syncDat.fire ){
+  when( io.latDat.fire ){
     inBusMuxValid := false.B
   } .elsewhen( ~inBusMuxValid ){
     inBusMuxValid := inBusSyncIO.map{ x => x.valid }.reduce(_|_)
diff --git a/src/main/scala/backBoard/CDROutBus.scala b/src/main/scala/backBoard/CDROutBus.scala
new file mode 100644
index 0000000..eb4f571
--- /dev/null
+++ b/src/main/scala/backBoard/CDROutBus.scala
@@ -0,0 +1,65 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class CDROutBusIO() extends Bundle{
+  val pkgDat = Flipped(Decoupled(new CDRData))
+  val dat    = Output(Bool())
+
+}
+
+class CDROutBus extends Module{
+  val io: CDROutBusIO = IO(new CDROutBusIO)
+
+  val isBusy = RegInit(false.B)
+  io.pkgDat.ready := ~isBusy
+  
+  val address  = Reg(UInt(6.W))
+  val register = Reg(UInt(8.W))
+  val data     = Reg(UInt(32.W))
+  val hash     = Reg(UInt(16.W))
+
+  val cnt = RegInit( 0.U(7.W) )
+
+
+  when( cnt === (1+6+8+32+16).U ){
+    isBusy := false.B
+  } .elsewhen( io.pkgDat.fire ){
+    isBusy := true.B
+
+    address  := io.pkgDat.bits.address
+    register := io.pkgDat.bits.register
+    data     := io.pkgDat.bits.data
+
+  }
+
+  when(io.pkgDat.fire){
+    cnt := 0.U
+  } .elsewhen( isBusy ){
+    cnt := cnt + 1.U
+  }
+
+
+
+  when( cnt === 0.U ){
+    io.dat := true.B
+  } .elsewhen( cnt >= (0 + 1).U && cnt < (6 + 1).U ){
+    io.dat := address(5)
+    address := address << 1
+  } .elsewhen( cnt >= (0 + 1 + 6).U && cnt < (8 + 1 + 6).U ){
+    io.dat := register(7)
+    register := register << 1
+  } .elsewhen( cnt >= (0 + 1 + 6 + 8).U && cnt < (32 + 1 + 6 + 8).U ){
+    io.dat := data(31)
+    data := data << 1
+  } .elsewhen( cnt >= (0 + 1 + 6 + 8 + 32).U && cnt < (16 + 1 + 6 + 8 + 32).U ){
+    io.dat := hash(15)
+    hash := hash << 1
+  } .otherwise{
+    io.dat := false.B
+  }
+
+}
+
diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index 659c4ba..92767f4 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -1,36 +1,31 @@
-package MAC
+package BACK
 
 import chisel3._
 import chisel3.util._
 
-// class LocalRegistersIO extends Bundle{
-//   val 
-// }
 
 
 
-class LocalRegisters(implicit p: Parameters) extends LazyModule{
 
-  val device = new SimpleDevice("slv",Seq("slv"))
-  val configNode = TLRegisterNode(
-    address = Seq(AddressSet(0x000L, 0x000000ffL)),
-    device = device,
-    concurrency = 1,
-    beatBytes = 32/8,
-    executable = true
-  )
+trait LocalRegisters { this: BackBoardSlvBase =>
 
-  lazy val module = new LocalRegImp(this){
+  val digitalDir = RegInit(0.U(32.W))
+  val digitalOut = RegInit(0.U(32.W))
+  val digitalIn  = WireDefault(0.U(32.W))
 
-    val digitalDir = RegInit(0.U(32.W))
-
-
-    configNode.regmap(
-      ( 0 << 2 ) -> 
-        RegFieldGroup("DigitalDir", Some("Digital IO Direction"), Seq(
-          RegField(32, digitalDir , RegFieldDesc( "digitalDir", "digitalDir", reset = Some(0))) ,
-        )),
-    )
+  registersRD := Mux1H(Seq(
+    (upStreamReq.io.latDat.bits.register === 0.U) -> digitalDir,
+    (upStreamReq.io.latDat.bits.register === 1.U) -> digitalIn,
+  ))
 
+  when( upStreamReq.io.latDat.fire & upStreamReq.io.latDat.bits.address(5,1) === io.localHost & upStreamReq.io.latDat.bits.address.extract(0) === 1.U ){
+    when(upStreamReq.io.latDat.bits.register === 0.U){
+      digitalDir := upStreamReq.io.latDat.bits.data
+    }
+    when(upStreamReq.io.latDat.bits.register === 1.U){
+      digitalOut := upStreamReq.io.latDat.bits.data
+    }
   }
+
+
 }
\ No newline at end of file
diff --git a/src/main/scala/backBoard/StatusControl.scala b/src/main/scala/backBoard/StatusControl.scala
deleted file mode 100644
index 3e1b44e..0000000
--- a/src/main/scala/backBoard/StatusControl.scala
+++ /dev/null
@@ -1,53 +0,0 @@
-package MAC
-
-import chisel3._
-import chisel3.util._
-
-
-class StatusControlIO extends Bundle{
-
-}
-
-
-class StatusControl(implicit p: Parameters) extends LazyModule{
-
-  val upStreamReq    = 
-  val downStreamResp = 
-
-  val upStreamResq   = 
-  val downStreamReq  = 
-
-
-  val register = LazyModule(new LocalRegisters)
-
-
-  lazy val module = new StatusControlImp(this){
-    val io: StatusControlIO = IO(new StatusControlIO)
-
-    def IDLE            = 0.U
-    def UPSTREAM_REQ    = 1.U
-    def DOWNSTREAM_REQ  = 2.U
-    def UPSTREAM_RESP   = 3.U
-    def DOWNSTREAM_RESP = 4.U
-
-    val stateNext = Wire( UInt(3.W) )
-    val stateCurr = RegNext(stateNext, 0.U)
-
-    stateNext := Mux1H(Seq(
-      (stateCurr === IDLE)            -> ,
-      (stateCurr === UPSTREAM_REQ)    -> ,
-      (stateCurr === DOWNSTREAM_REQ)  -> ,
-      (stateCurr === UPSTREAM_RESP)   -> ,
-      (stateCurr === DOWNSTREAM_RESP) -> ,
-    ))
-
-
-
-
-
-
-
-
-
-  }
-}
\ No newline at end of file
diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala
index f6ee24c..37ac971 100644
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -1,6 +1,8 @@
 package test
 
 import MAC._
+import BACK._
+
 import chisel3._
 import chisel3.stage._
 import freechips.rocketchip.diplomacy._
@@ -10,19 +12,20 @@ import org.chipsalliance.cde.config._
 
 
 object testModule extends App {
-  // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
-  //     ChiselGeneratorAnnotation(() => {
-  //   new Mac
-  // })
-  //   ))
-  val cfg = new MacCfg
-
-  (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
       ChiselGeneratorAnnotation(() => {
-    val soc = LazyModule(new MacTest()(cfg))
-    soc.module
+    new BackBoardSlv
   })
-  ))
+    ))
+
+  // val cfg = new MacCfg
+
+  // (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(
+  //     ChiselGeneratorAnnotation(() => {
+  //   val soc = LazyModule(new MacTest()(cfg))
+  //   soc.module
+  // })
+  // ))
 
 
 }