backplaneslv compile pass

Signed-off-by: Ruige <295054118@whut.edu.cn>

src/main/scala/backBoard/LocalRegisters.scala

@@ -1,36 +1,31 @@
-package MAC
+package BACK
 
 import chisel3._
 import chisel3.util._
 
-// class LocalRegistersIO extends Bundle{
-//   val 
-// }
 
 
 
-class LocalRegisters(implicit p: Parameters) extends LazyModule{
 
-  val device = new SimpleDevice("slv",Seq("slv"))
-  val configNode = TLRegisterNode(
-    address = Seq(AddressSet(0x000L, 0x000000ffL)),
-    device = device,
-    concurrency = 1,
-    beatBytes = 32/8,
-    executable = true
-  )
+trait LocalRegisters { this: BackBoardSlvBase =>
 
-  lazy val module = new LocalRegImp(this){
+  val digitalDir = RegInit(0.U(32.W))
+  val digitalOut = RegInit(0.U(32.W))
+  val digitalIn  = WireDefault(0.U(32.W))
 
-    val digitalDir = RegInit(0.U(32.W))
-
-
-    configNode.regmap(
-      ( 0 << 2 ) -> 
-        RegFieldGroup("DigitalDir", Some("Digital IO Direction"), Seq(
-          RegField(32, digitalDir , RegFieldDesc( "digitalDir", "digitalDir", reset = Some(0))) ,
-        )),
-    )
+  registersRD := Mux1H(Seq(
+    (upStreamReq.io.latDat.bits.register === 0.U) -> digitalDir,
+    (upStreamReq.io.latDat.bits.register === 1.U) -> digitalIn,
+  ))
 
+  when( upStreamReq.io.latDat.fire & upStreamReq.io.latDat.bits.address(5,1) === io.localHost & upStreamReq.io.latDat.bits.address.extract(0) === 1.U ){
+    when(upStreamReq.io.latDat.bits.register === 0.U){
+      digitalDir := upStreamReq.io.latDat.bits.data
+    }
+    when(upStreamReq.io.latDat.bits.register === 1.U){
+      digitalOut := upStreamReq.io.latDat.bits.data
+    }
   }
+
+
 }