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新需求 din寄存器更新

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RuigeLee
2024-09-02 17:46:14 +08:00
parent aa5a8f9a95
commit 838729a694
2 changed files with 15 additions and 12 deletions
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2
rocket-chip

Submodule rocket-chip updated: 15e7cfb7b7...7cb39049b9

25
src/main/scala/backBoard/Dout16.scala
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@@ -41,19 +41,22 @@ with BackBoardSlvOut16{
outRegSync := RegEnable( outReg, 0.U, isUpdate ) outRegSync := RegEnable( outReg, 0.U, isUpdate )
when( statusPage === 0.U ){ when( statusPage === 0.U ){
upReg(2) := outReg(7,0) upReg(2) := Cat( 0.U(7.W), ~v24Det )
upReg(3) := outReg(15,8) upReg(3) := 0.U
upReg(4) := Cat( ~flt(1), ~flt(0) ) upReg(4) := Cat( 0.U(7.W), ~flt(0) )
upReg(5) := Cat( ~v24Det, 0.U(7.W) ) upReg(5) := 0.U
} upReg(6) := Cat( 0.U(7.W), ~flt(1) )
upReg(7) := 0.U
when( statusPage === 1.U ){ upReg(8) := mthodReg(7,0)
upReg(2) := RegEnable(downRegTemp(2).extract(0), isCrcPass & downRegTemp(0)(3,0) === 1.U) upReg(9) := mthodReg(15,8)
upReg(10) := valueReg(7,0)
upReg(11) := valueReg(15,8)
upReg(12) := outReg(7,0)
upReg(13) := outReg(15,8)
upReg(4) := mthodReg(7,0)
upReg(5) := mthodReg(15,8)
upReg(6) := valueReg(7,0)
upReg(7) := valueReg(15,8)
} }