From 838729a69454866c66aa5974e9a10c67924acdaf Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Mon, 2 Sep 2024 17:46:14 +0800
Subject: [PATCH] =?UTF-8?q?=E6=96=B0=E9=9C=80=E6=B1=82=20din=E5=AF=84?=
 =?UTF-8?q?=E5=AD=98=E5=99=A8=E6=9B=B4=E6=96=B0?=
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---
 rocket-chip                           |  2 +-
 src/main/scala/backBoard/Dout16.scala | 25 ++++++++++++++-----------
 2 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/rocket-chip b/rocket-chip
index 15e7cfb..7cb3904 160000
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit 15e7cfb7b7e8645b59916d0385c96493c230e7f3
+Subproject commit 7cb39049b9778bfc9dd4f66bb7c4abaede9606c9
diff --git a/src/main/scala/backBoard/Dout16.scala b/src/main/scala/backBoard/Dout16.scala
index d75c217..3ba70af 100644
--- a/src/main/scala/backBoard/Dout16.scala
+++ b/src/main/scala/backBoard/Dout16.scala
@@ -41,19 +41,22 @@ with BackBoardSlvOut16{
   outRegSync := RegEnable( outReg, 0.U, isUpdate )
 
   when( statusPage === 0.U ){
-    upReg(2) := outReg(7,0)
-    upReg(3) := outReg(15,8)
-    upReg(4) := Cat( ~flt(1), ~flt(0) )
-    upReg(5) := Cat( ~v24Det, 0.U(7.W) )
-  }
+    upReg(2) := Cat( 0.U(7.W), ~v24Det )
+    upReg(3) := 0.U
+    upReg(4) := Cat( 0.U(7.W), ~flt(0) )
+    upReg(5) := 0.U
+    upReg(6) := Cat( 0.U(7.W), ~flt(1) )
+    upReg(7) := 0.U
 
-  when( statusPage === 1.U ){
-    upReg(2) := RegEnable(downRegTemp(2).extract(0), isCrcPass & downRegTemp(0)(3,0) === 1.U)
+    upReg(8) := mthodReg(7,0)
+    upReg(9) := mthodReg(15,8)
+
+    upReg(10) := valueReg(7,0)
+    upReg(11) := valueReg(15,8)
+
+    upReg(12) := outReg(7,0)
+    upReg(13) := outReg(15,8)
 
-    upReg(4) := mthodReg(7,0)
-    upReg(5) := mthodReg(15,8)
-    upReg(6) := valueReg(7,0)
-    upReg(7) := valueReg(15,8)
   }