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代码逻辑优化，增强保护

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This commit is contained in:
Ruige Lee
2025-06-19 14:30:47 +08:00
parent 47ff36aa69
commit 8149c48100
1 changed files with 69 additions and 30 deletions
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71
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -577,7 +577,11 @@ trait SlaveParserRW{ this: SlaveParserBase =>
}
)
when( isUpLgcAddrrAcquireTrans ){ //装填计数器
when( isUpLgcAddrrAcquireTrans & (
(upRecParser.io.subMsgReq.fire & (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex) |
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex ))
)){ //装填计数器
upTransLenCnt := acquireUpTransLen
} .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U ){
upTransLenCnt := upTransLenCnt - 1.U
@@ -588,11 +592,15 @@ trait SlaveParserRW{ this: SlaveParserBase =>
(upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex
)){//组合逻辑
logicAddrrNext := Cat( upRecParser.io.subMsgReq.bits.devIndex, upRecParser.io.subMsgReq.bits.address )
} .elsewhen( upRecParser.io.data.fire & (
} .elsewhen( upRecParser.io.data.fire){
when(
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).isLgcIndex ) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).isLgcIndex )
) ){//组合逻辑
){//组合逻辑
logicAddrrNext := logicAddrr + 1.U
} .otherwise{
logicAddrrNext := 0.U
}
} .otherwise{//组合逻辑
logicAddrrNext := logicAddrr
}
@@ -623,31 +631,62 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val isLvdsEnR = isSeqRead | isLgcRead
when( upRecParser.io.subMsgReq.fire){
// when( upRecParser.io.subMsgReq.fire){
// when(
// ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) |
// ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
// ){
// addrr := upRecParser.io.subMsgReq.bits.address
// } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
// addrr := acquireUpPhyAddrr
// }
// } .elsewhen( isUpLgcAddrrAcquireTrans ){
// when( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
// addrr := acquireUpPhyAddrr
// }
// }
// .elsewhen( isLvdsEnR ){
// assert(~isUpLgcAddrrAcquireTrans)
// when(
// ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) |
// ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
// ){
// addrr := addrr + 1.U
// } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
// addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U )
// }
// }
when(
((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) |
( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
){
when( upRecParser.io.subMsgReq.fire){
addrr := upRecParser.io.subMsgReq.bits.address
} .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
addrr := acquireUpPhyAddrr
} .elsewhen(isLvdsEnR){
addrr := addrr + 1.U
}
} .elsewhen( isUpLgcAddrrAcquireTrans ){
when( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
when(
(upRecParser.io.subMsgReq.fire & (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex) |
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex ))
){
addrr := acquireUpPhyAddrr
}
}
.elsewhen( isLvdsEnR ){
} .elsewhen( isLvdsEnR & (
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) |
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex ))
)){
assert(~isUpLgcAddrrAcquireTrans)
when(
((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) |
( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
){
addrr := addrr + 1.U
} .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U )
}
}
val upStreamData = Mux1H(Seq(
isRDReg -> io.lvds.datar,