From 8149c48100c04b794da2071b17b1d04aa66930ce Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 19 Jun 2025 14:30:47 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BB=A3=E7=A0=81=E9=80=BB=E8=BE=91=E4=BC=98?= =?UTF-8?q?=E5=8C=96=EF=BC=8C=E5=A2=9E=E5=BC=BA=E4=BF=9D=E6=8A=A4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 99 +++++++++++++------ 1 file changed, 69 insertions(+), 30 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 61bd9bb..d5bbfa8 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -577,9 +577,13 @@ trait SlaveParserRW{ this: SlaveParserBase => } ) - when( isUpLgcAddrrAcquireTrans ){ //装填计数器 + when( isUpLgcAddrrAcquireTrans & ( + (upRecParser.io.subMsgReq.fire & (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex) | + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex )) + )){ //装填计数器 upTransLenCnt := acquireUpTransLen - } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U){ + } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U ){ upTransLenCnt := upTransLenCnt - 1.U } @@ -588,11 +592,15 @@ trait SlaveParserRW{ this: SlaveParserBase => (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex )){//组合逻辑 logicAddrrNext := Cat( upRecParser.io.subMsgReq.bits.devIndex, upRecParser.io.subMsgReq.bits.address ) - } .elsewhen( upRecParser.io.data.fire & ( - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).isLgcIndex ) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).isLgcIndex ) - ) ){//组合逻辑 - logicAddrrNext := logicAddrr + 1.U + } .elsewhen( upRecParser.io.data.fire){ + when( + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).isLgcIndex ) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).isLgcIndex ) + ){//组合逻辑 + logicAddrrNext := logicAddrr + 1.U + } .otherwise{ + logicAddrrNext := 0.U + } } .otherwise{//组合逻辑 logicAddrrNext := logicAddrr } @@ -623,38 +631,69 @@ trait SlaveParserRW{ this: SlaveParserBase => val isLvdsEnR = isSeqRead | isLgcRead - when( upRecParser.io.subMsgReq.fire){ - when( - ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | - ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) - ){ + + + + + // when( upRecParser.io.subMsgReq.fire){ + // when( + // ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | + // ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) + // ){ + // addrr := upRecParser.io.subMsgReq.bits.address + // } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + // addrr := acquireUpPhyAddrr + // } + // } .elsewhen( isUpLgcAddrrAcquireTrans ){ + // when( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + // addrr := acquireUpPhyAddrr + // } + // } + // .elsewhen( isLvdsEnR ){ + // assert(~isUpLgcAddrrAcquireTrans) + // when( + // ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | + // ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) + // ){ + // addrr := addrr + 1.U + // } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + // addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) + // } + // } + + when( + ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | + ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) + ){ + when( upRecParser.io.subMsgReq.fire){ addrr := upRecParser.io.subMsgReq.bits.address - } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ - addrr := acquireUpPhyAddrr + } .elsewhen(isLvdsEnR){ + addrr := addrr + 1.U } } .elsewhen( isUpLgcAddrrAcquireTrans ){ - when( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + when( + (upRecParser.io.subMsgReq.fire & (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex) | + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex )) + ){ addrr := acquireUpPhyAddrr } - } - .elsewhen( isLvdsEnR ){ + } .elsewhen( isLvdsEnR & ( + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex )) + )){ assert(~isUpLgcAddrrAcquireTrans) - when( - ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | - ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) - ){ - addrr := addrr + 1.U - } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ - addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) - } + addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) } + + val upStreamData = Mux1H(Seq( - isRDReg -> io.lvds.datar, - isRDSM1 -> io.sram_r(0).datar, - isRDSM3 -> io.sram_r(1).datar, - isRDSM5 -> io.sram_r(2).datar, - isRDSM7 -> io.sram_r(3).datar, + isRDReg -> io.lvds.datar, + isRDSM1 -> io.sram_r(0).datar, + isRDSM3 -> io.sram_r(1).datar, + isRDSM5 -> io.sram_r(2).datar, + isRDSM7 -> io.sram_r(3).datar, ))