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高云FPGA：SR寄存器高3bits开放使用

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This commit is contained in:
Ruige Lee
2025-02-28 10:52:07 +08:00
parent 699786b7d1
commit 7f123244be
1 changed files with 6 additions and 2 deletions
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6
src/main/scala/backBoard/LocalRegisters.scala
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@@ -24,6 +24,10 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
val statusLE = RegInit(false.B) val statusLE = RegInit(false.B)
val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass ) val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass )
val statusNone = ~ShiftRegister(io.isLast, 2) val statusNone = ~ShiftRegister(io.isLast, 2)
val customData = for( i <- 0 until 3 ) yield {
RegEnable( downRegTemp(1).extract(5+i), false.B, isCrcPass )
}
val page15reg2 = WireDefault(0.U(8.W)) val page15reg2 = WireDefault(0.U(8.W))
val page15reg3 = WireDefault(0.U(8.W)) val page15reg3 = WireDefault(0.U(8.W))
@@ -35,7 +39,7 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
val page15reg9 = WireDefault(0.U(8.W)) val page15reg9 = WireDefault(0.U(8.W))
upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage ) upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage )
upReg(1) := Cat( statusNone, statusSync, statusLE, statusER, statusPR.extract(1) ) upReg(1) := Cat( customData(2), customData(1), customData(0), statusNone, statusSync, statusLE, statusER, statusPR.extract(1) )
when( statusPage === 15.U ){ when( statusPage === 15.U ){
upReg(2) := page15reg2 upReg(2) := page15reg2