diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index 2677006..5c20db9 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -23,7 +23,11 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
   val statusER   = RegInit(false.B)
   val statusLE   = RegInit(false.B)
   val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass )
-  val statusNone = ~ShiftRegister(io.isLast, 2) 
+  val statusNone = ~ShiftRegister(io.isLast, 2)
+  val customData = for( i <- 0 until 3 ) yield {
+    RegEnable( downRegTemp(1).extract(5+i), false.B, isCrcPass )
+  }
+
 
   val page15reg2 = WireDefault(0.U(8.W))
   val page15reg3 = WireDefault(0.U(8.W))
@@ -35,7 +39,7 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
   val page15reg9 = WireDefault(0.U(8.W))
 
   upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage )
-  upReg(1) := Cat( statusNone, statusSync, statusLE, statusER, statusPR.extract(1) )
+  upReg(1) := Cat( customData(2), customData(1), customData(0), statusNone, statusSync, statusLE, statusER, statusPR.extract(1) )
 
   when( statusPage === 15.U ){
     upReg(2) := page15reg2