启用中断，开始调中断软件
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RuigeLee
@@ -25,19 +25,21 @@ main:
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li x6, 32 # 设置循环次数
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1:
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beqz x15, 2f # 如果x10为0，则跳到2
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beqz x15, 3f # 如果x10为0，则跳到3
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2:
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li x15, 0 # 清标志位
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lw x7, 0(x5) # 读取cdr_0_tx_status的值
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andi x7, x7, 0x2 # 检查第1比特（位1）
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beqz x7, 1b # 如果第1比特为0，则回到1处继续循环
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beqz x7, 2b # 如果第1比特为0，则回到2处继续循环
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2:
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3:
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# 向cdr_0_tx_txFifo地址写入0x55，循环32次
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sw x6, 8(x5) # 向cdr_0_tx_txFifo写入0x55
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addi x6, x6, -1 # 递减计数器
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bnez x6, 1b # 如果计数器不为0，则继续循环
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addi x6, x6, -1 # 递减计数器
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bnez x6, 1b # 如果计数器不为0，则继续循环
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3:
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j 3b
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4:
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j 4b
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@@ -3,314 +3,52 @@
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#include "custom_ops.S"
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.extern main
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.globl _prog_start
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.section .text.init
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.section .text
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.globl _prog_start
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.global irq
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.extern main
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/* Interrupt handler
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**********************************/
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_prog_start:
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li x15, 0
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picorv32_maskirq_insn(zero, zero)
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call main
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.balign 16
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irq_vec:
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/* save registers */
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picorv32_setq_insn(q2, x1)
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picorv32_setq_insn(q3, x2)
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lui x1, %hi(irq_regs)
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addi x1, x1, %lo(irq_regs)
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picorv32_getq_insn(x2, q0)
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sw x2, 0*4(x1)
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picorv32_getq_insn(x2, q2)
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sw x2, 1*4(x1)
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picorv32_getq_insn(x2, q3)
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sw x2, 2*4(x1)
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#ifdef ENABLE_FASTIRQ
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sw x5, 5*4(x1)
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sw x6, 6*4(x1)
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sw x7, 7*4(x1)
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sw x10, 10*4(x1)
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sw x11, 11*4(x1)
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sw x12, 12*4(x1)
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sw x13, 13*4(x1)
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sw x14, 14*4(x1)
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sw x15, 15*4(x1)
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sw x16, 16*4(x1)
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sw x17, 17*4(x1)
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sw x28, 28*4(x1)
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sw x29, 29*4(x1)
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sw x30, 30*4(x1)
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sw x31, 31*4(x1)
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#else
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sw x3, 3*4(x1)
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sw x4, 4*4(x1)
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sw x5, 5*4(x1)
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sw x6, 6*4(x1)
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sw x7, 7*4(x1)
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sw x8, 8*4(x1)
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sw x9, 9*4(x1)
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sw x10, 10*4(x1)
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sw x11, 11*4(x1)
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sw x12, 12*4(x1)
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sw x13, 13*4(x1)
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sw x14, 14*4(x1)
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sw x15, 15*4(x1)
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sw x16, 16*4(x1)
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sw x17, 17*4(x1)
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sw x18, 18*4(x1)
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sw x19, 19*4(x1)
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sw x20, 20*4(x1)
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sw x21, 21*4(x1)
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sw x22, 22*4(x1)
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sw x23, 23*4(x1)
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sw x24, 24*4(x1)
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sw x25, 25*4(x1)
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sw x26, 26*4(x1)
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sw x27, 27*4(x1)
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sw x28, 28*4(x1)
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sw x29, 29*4(x1)
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sw x30, 30*4(x1)
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sw x31, 31*4(x1)
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#endif
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li gp, 1;
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ecall
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/* call interrupt handler C function */
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lui sp, %hi(irq_stack)
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addi sp, sp, %lo(irq_stack)
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// arg0 = address of regs
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lui a0, %hi(irq_regs)
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addi a0, a0, %lo(irq_regs)
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// arg1 = interrupt type
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picorv32_getq_insn(a1, q1)
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// call to C function
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# jal ra, irq
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/* restore registers */
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// new irq_regs address returned from C code in a0
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addi x1, a0, 0
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lw x2, 0*4(x1)
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picorv32_setq_insn(q0, x2)
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lw x2, 1*4(x1)
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picorv32_setq_insn(q1, x2)
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lw x2, 2*4(x1)
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picorv32_setq_insn(q2, x2)
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#ifdef ENABLE_FASTIRQ
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lw x5, 5*4(x1)
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lw x6, 6*4(x1)
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lw x7, 7*4(x1)
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lw x10, 10*4(x1)
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lw x11, 11*4(x1)
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lw x12, 12*4(x1)
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lw x13, 13*4(x1)
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lw x14, 14*4(x1)
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lw x15, 15*4(x1)
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lw x16, 16*4(x1)
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lw x17, 17*4(x1)
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lw x28, 28*4(x1)
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lw x29, 29*4(x1)
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lw x30, 30*4(x1)
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lw x31, 31*4(x1)
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#else
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lw x3, 3*4(x1)
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lw x4, 4*4(x1)
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lw x5, 5*4(x1)
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lw x6, 6*4(x1)
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lw x7, 7*4(x1)
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lw x8, 8*4(x1)
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lw x9, 9*4(x1)
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lw x10, 10*4(x1)
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lw x11, 11*4(x1)
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lw x12, 12*4(x1)
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lw x13, 13*4(x1)
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lw x14, 14*4(x1)
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lw x15, 15*4(x1)
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lw x16, 16*4(x1)
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lw x17, 17*4(x1)
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lw x18, 18*4(x1)
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lw x19, 19*4(x1)
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lw x20, 20*4(x1)
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lw x21, 21*4(x1)
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lw x22, 22*4(x1)
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lw x23, 23*4(x1)
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lw x24, 24*4(x1)
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lw x25, 25*4(x1)
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lw x26, 26*4(x1)
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lw x27, 27*4(x1)
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lw x28, 28*4(x1)
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lw x29, 29*4(x1)
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lw x30, 30*4(x1)
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lw x31, 31*4(x1)
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#endif
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picorv32_getq_insn(x1, q1)
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picorv32_getq_insn(x2, q2)
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.balign 32
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.section .trap_entry
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trap_entry:
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# q0 return address
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# q1 bitmask of all IRQ to be handled, may be more than one IRQ
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# q2 q3 unused, can be use as temp storage register
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# q寄存器已经禁用， Without the q-registers, the irq return address will be stored in x3 (gp) and the IRQ bitmask in x4 (tp),
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addi x15, x4, 0
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picorv32_retirq_insn()
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.balign 0x200
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irq_regs:
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// registers are saved to this memory region during interrupt handling
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// the program counter is saved as register 0
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.fill 32,4
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// stack for the interrupt handler
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.fill 128,4
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irq_stack:
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_prog_start:
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10,0
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li x11,0
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li x12,0
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li x13,0
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li x14,0
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li x15,0
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li x16,0
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li x17,0
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li x18,0
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li x19,0
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li x20,0
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li x21,0
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li x22,0
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li x23,0
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li x24,0
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li x25,0
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li x26,0
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li x27,0
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li x28,0
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li x29,0
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li x30,0
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li x31,0
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li sp, 0x80010000
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call main
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li gp, 1;
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ecall
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trap_entry:
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addi sp, sp, -136
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sw x1, 1* 4(sp)
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sw x2, 2* 4(sp)
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sw x3, 3* 4(sp)
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sw x4, 4* 4(sp)
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sw x5, 5* 4(sp)
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sw x6, 6* 4(sp)
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sw x7, 7* 4(sp)
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sw x8, 8* 4(sp)
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sw x9, 9* 4(sp)
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sw x10, 10*4(sp)
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sw x11, 11*4(sp)
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sw x12, 12*4(sp)
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sw x13, 13*4(sp)
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sw x14, 14*4(sp)
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sw x15, 15*4(sp)
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sw x16, 16*4(sp)
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sw x17, 17*4(sp)
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sw x18, 18*4(sp)
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sw x19, 19*4(sp)
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sw x20, 20*4(sp)
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sw x21, 21*4(sp)
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sw x22, 22*4(sp)
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sw x23, 23*4(sp)
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sw x24, 24*4(sp)
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sw x25, 25*4(sp)
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sw x26, 26*4(sp)
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sw x27, 27*4(sp)
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sw x28, 28*4(sp)
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sw x29, 29*4(sp)
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sw x30, 30*4(sp)
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sw x31, 31*4(sp)
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# csrr a0, mcause
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# csrr a1, mepc
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mv a2, sp
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# jal handle_trap
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# csrw mepc, a0
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# li t0, MSTATUS_MPP
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# csrs mstatus, t0
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lw x1, 1 *4(sp)
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lw x2, 2 *4(sp)
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lw x3, 3 *4(sp)
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lw x4, 4 *4(sp)
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lw x5, 5 *4(sp)
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lw x6, 6 *4(sp)
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lw x7, 7 *4(sp)
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lw x8, 8 *4(sp)
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lw x9, 9 *4(sp)
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lw x10, 10*4(sp)
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lw x11, 11*4(sp)
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lw x12, 12*4(sp)
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lw x13, 13*4(sp)
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lw x14, 14*4(sp)
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lw x15, 15*4(sp)
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lw x16, 16*4(sp)
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lw x17, 17*4(sp)
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lw x18, 18*4(sp)
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lw x19, 19*4(sp)
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lw x20, 20*4(sp)
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lw x21, 21*4(sp)
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lw x22, 22*4(sp)
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lw x23, 23*4(sp)
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lw x24, 24*4(sp)
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lw x25, 25*4(sp)
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lw x26, 26*4(sp)
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lw x27, 27*4(sp)
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lw x28, 28*4(sp)
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lw x29, 29*4(sp)
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lw x30, 30*4(sp)
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lw x31, 31*4(sp)
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addi sp, sp, 136
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mret
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