diff --git a/Makefile b/Makefile index 311081d..20be45c 100644 --- a/Makefile +++ b/Makefile @@ -88,10 +88,15 @@ sw: riscv64-unknown-elf-objcopy -O binary ./tb/sw/build/test.elf ./tb/sw/build/test.bin - riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata ./tb/sw/build/test.elf > ./tb/sw/build/test.dump + # riscv64-unknown-elf-objdump -h ./tb/sw/build/test.elf > ./tb/sw/build/test.dump + riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/test.elf > ./tb/sw/build/test.dump - riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/test.elf ./tb/sw/build/test.verilog + # riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf + + riscv64-unknown-elf-readelf -a ./tb/sw/build/test.elf + riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf + riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/test.elf ./tb/sw/build/test.verilog sed -i 's/@800/@000/g' ./tb/sw/build/test.verilog fst: diff --git a/src/main/resources/picorv32.v b/src/main/resources/picorv32.v index 31446ef..e761f6b 100644 --- a/src/main/resources/picorv32.v +++ b/src/main/resources/picorv32.v @@ -74,15 +74,15 @@ module picorv32 #( parameter [ 0:0] ENABLE_MUL = 0, parameter [ 0:0] ENABLE_FAST_MUL = 0, parameter [ 0:0] ENABLE_DIV = 0, - parameter [ 0:0] ENABLE_IRQ = 0, - parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ = 1, + parameter [ 0:0] ENABLE_IRQ_QREGS = 0, parameter [ 0:0] ENABLE_IRQ_TIMER = 1, parameter [ 0:0] ENABLE_TRACE = 0, parameter [ 0:0] REGS_INIT_ZERO = 0, parameter [31:0] MASKED_IRQ = 32'h 0000_0000, parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, parameter [31:0] PROGADDR_RESET = 32'h 8000_0000, - parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] PROGADDR_IRQ = 32'h 8000_0800, parameter [31:0] STACKADDR = 32'h ffff_ffff ) ( input clk, resetn, diff --git a/src/main/scala/backBoard/pico/picorv32.scala b/src/main/scala/backBoard/pico/picorv32.scala index 7e47d81..790071f 100644 --- a/src/main/scala/backBoard/pico/picorv32.scala +++ b/src/main/scala/backBoard/pico/picorv32.scala @@ -10,7 +10,7 @@ import chisel3.experimental._ class picorv32 extends BlackBox() with HasBlackBoxResource { val io = IO(new Bundle { val clk = Input(Bool()) - val resetn = Input(Bool()) + val resetn = Input(Bool()) val trap = Output(Bool()) val mem_valid = Output(Bool()) diff --git a/tb/sw/linker.lds b/tb/sw/linker.lds index d6e3bb7..e918338 100644 --- a/tb/sw/linker.lds +++ b/tb/sw/linker.lds @@ -36,4 +36,7 @@ SECTIONS *(.rodata*) _RODATA_END_ = .; } + + . = 0x80000800; + .trap_entry : { *(.trap_entry)} } diff --git a/tb/sw/src/main.S b/tb/sw/src/main.S index 2237ce4..6ca28c7 100644 --- a/tb/sw/src/main.S +++ b/tb/sw/src/main.S @@ -25,19 +25,21 @@ main: li x6, 32 # 设置循环次数 1: - beqz x15, 2f # 如果x10为0，则跳到2 + beqz x15, 3f # 如果x10为0，则跳到3 +2: + li x15, 0 # 清标志位 lw x7, 0(x5) # 读取cdr_0_tx_status的值 andi x7, x7, 0x2 # 检查第1比特（位1） - beqz x7, 1b # 如果第1比特为0，则回到1处继续循环 + beqz x7, 2b # 如果第1比特为0，则回到2处继续循环 -2: +3: # 向cdr_0_tx_txFifo地址写入0x55，循环32次 sw x6, 8(x5) # 向cdr_0_tx_txFifo写入0x55 - addi x6, x6, -1 # 递减计数器 - bnez x6, 1b # 如果计数器不为0，则继续循环 + addi x6, x6, -1 # 递减计数器 + bnez x6, 1b # 如果计数器不为0，则继续循环 -3: - j 3b +4: + j 4b diff --git a/tb/sw/src/startup.S b/tb/sw/src/startup.S index 408b3a8..1e6ffa1 100644 --- a/tb/sw/src/startup.S +++ b/tb/sw/src/startup.S @@ -3,314 +3,52 @@ #include "custom_ops.S" +.extern main +.globl _prog_start +.section .text.init - .section .text - .globl _prog_start - .global irq - .extern main -/* Interrupt handler - **********************************/ +_prog_start: + li x15, 0 + picorv32_maskirq_insn(zero, zero) + call main -.balign 16 -irq_vec: - /* save registers */ - - picorv32_setq_insn(q2, x1) - picorv32_setq_insn(q3, x2) - - lui x1, %hi(irq_regs) - addi x1, x1, %lo(irq_regs) - - picorv32_getq_insn(x2, q0) - sw x2, 0*4(x1) - - picorv32_getq_insn(x2, q2) - sw x2, 1*4(x1) - - picorv32_getq_insn(x2, q3) - sw x2, 2*4(x1) - -#ifdef ENABLE_FASTIRQ - sw x5, 5*4(x1) - sw x6, 6*4(x1) - sw x7, 7*4(x1) - sw x10, 10*4(x1) - sw x11, 11*4(x1) - sw x12, 12*4(x1) - sw x13, 13*4(x1) - sw x14, 14*4(x1) - sw x15, 15*4(x1) - sw x16, 16*4(x1) - sw x17, 17*4(x1) - sw x28, 28*4(x1) - sw x29, 29*4(x1) - sw x30, 30*4(x1) - sw x31, 31*4(x1) -#else - sw x3, 3*4(x1) - sw x4, 4*4(x1) - sw x5, 5*4(x1) - sw x6, 6*4(x1) - sw x7, 7*4(x1) - sw x8, 8*4(x1) - sw x9, 9*4(x1) - sw x10, 10*4(x1) - sw x11, 11*4(x1) - sw x12, 12*4(x1) - sw x13, 13*4(x1) - sw x14, 14*4(x1) - sw x15, 15*4(x1) - sw x16, 16*4(x1) - sw x17, 17*4(x1) - sw x18, 18*4(x1) - sw x19, 19*4(x1) - sw x20, 20*4(x1) - sw x21, 21*4(x1) - sw x22, 22*4(x1) - sw x23, 23*4(x1) - sw x24, 24*4(x1) - sw x25, 25*4(x1) - sw x26, 26*4(x1) - sw x27, 27*4(x1) - sw x28, 28*4(x1) - sw x29, 29*4(x1) - sw x30, 30*4(x1) - sw x31, 31*4(x1) -#endif + li gp, 1; + ecall - /* call interrupt handler C function */ - - lui sp, %hi(irq_stack) - addi sp, sp, %lo(irq_stack) - - // arg0 = address of regs - lui a0, %hi(irq_regs) - addi a0, a0, %lo(irq_regs) - - // arg1 = interrupt type - picorv32_getq_insn(a1, q1) - // call to C function - # jal ra, irq - /* restore registers */ - // new irq_regs address returned from C code in a0 - addi x1, a0, 0 - lw x2, 0*4(x1) - picorv32_setq_insn(q0, x2) - lw x2, 1*4(x1) - picorv32_setq_insn(q1, x2) - lw x2, 2*4(x1) - picorv32_setq_insn(q2, x2) -#ifdef ENABLE_FASTIRQ - lw x5, 5*4(x1) - lw x6, 6*4(x1) - lw x7, 7*4(x1) - lw x10, 10*4(x1) - lw x11, 11*4(x1) - lw x12, 12*4(x1) - lw x13, 13*4(x1) - lw x14, 14*4(x1) - lw x15, 15*4(x1) - lw x16, 16*4(x1) - lw x17, 17*4(x1) - lw x28, 28*4(x1) - lw x29, 29*4(x1) - lw x30, 30*4(x1) - lw x31, 31*4(x1) -#else - lw x3, 3*4(x1) - lw x4, 4*4(x1) - lw x5, 5*4(x1) - lw x6, 6*4(x1) - lw x7, 7*4(x1) - lw x8, 8*4(x1) - lw x9, 9*4(x1) - lw x10, 10*4(x1) - lw x11, 11*4(x1) - lw x12, 12*4(x1) - lw x13, 13*4(x1) - lw x14, 14*4(x1) - lw x15, 15*4(x1) - lw x16, 16*4(x1) - lw x17, 17*4(x1) - lw x18, 18*4(x1) - lw x19, 19*4(x1) - lw x20, 20*4(x1) - lw x21, 21*4(x1) - lw x22, 22*4(x1) - lw x23, 23*4(x1) - lw x24, 24*4(x1) - lw x25, 25*4(x1) - lw x26, 26*4(x1) - lw x27, 27*4(x1) - lw x28, 28*4(x1) - lw x29, 29*4(x1) - lw x30, 30*4(x1) - lw x31, 31*4(x1) -#endif - picorv32_getq_insn(x1, q1) - picorv32_getq_insn(x2, q2) + + + + + + + + + + +.balign 32 +.section .trap_entry +trap_entry: + # q0 return address + # q1 bitmask of all IRQ to be handled, may be more than one IRQ + # q2 q3 unused, can be use as temp storage register + + # q寄存器已经禁用， Without the q-registers, the irq return address will be stored in x3 (gp) and the IRQ bitmask in x4 (tp), + + addi x15, x4, 0 picorv32_retirq_insn() -.balign 0x200 -irq_regs: - // registers are saved to this memory region during interrupt handling - // the program counter is saved as register 0 - .fill 32,4 - // stack for the interrupt handler - .fill 128,4 -irq_stack: - - - - - - - - - - - - - - - - - - - -_prog_start: - - li x1, 0 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - li x7, 0 - li x8, 0 - li x9, 0 - li x10,0 - li x11,0 - li x12,0 - li x13,0 - li x14,0 - li x15,0 - li x16,0 - li x17,0 - li x18,0 - li x19,0 - li x20,0 - li x21,0 - li x22,0 - li x23,0 - li x24,0 - li x25,0 - li x26,0 - li x27,0 - li x28,0 - li x29,0 - li x30,0 - li x31,0 - - li sp, 0x80010000 - - - call main - - li gp, 1; - ecall - -trap_entry: - addi sp, sp, -136 - - sw x1, 1* 4(sp) - sw x2, 2* 4(sp) - sw x3, 3* 4(sp) - sw x4, 4* 4(sp) - sw x5, 5* 4(sp) - sw x6, 6* 4(sp) - sw x7, 7* 4(sp) - sw x8, 8* 4(sp) - sw x9, 9* 4(sp) - sw x10, 10*4(sp) - sw x11, 11*4(sp) - sw x12, 12*4(sp) - sw x13, 13*4(sp) - sw x14, 14*4(sp) - sw x15, 15*4(sp) - sw x16, 16*4(sp) - sw x17, 17*4(sp) - sw x18, 18*4(sp) - sw x19, 19*4(sp) - sw x20, 20*4(sp) - sw x21, 21*4(sp) - sw x22, 22*4(sp) - sw x23, 23*4(sp) - sw x24, 24*4(sp) - sw x25, 25*4(sp) - sw x26, 26*4(sp) - sw x27, 27*4(sp) - sw x28, 28*4(sp) - sw x29, 29*4(sp) - sw x30, 30*4(sp) - sw x31, 31*4(sp) - - # csrr a0, mcause - # csrr a1, mepc - mv a2, sp - # jal handle_trap - # csrw mepc, a0 - - - # li t0, MSTATUS_MPP - # csrs mstatus, t0 - - lw x1, 1 *4(sp) - lw x2, 2 *4(sp) - lw x3, 3 *4(sp) - lw x4, 4 *4(sp) - lw x5, 5 *4(sp) - lw x6, 6 *4(sp) - lw x7, 7 *4(sp) - lw x8, 8 *4(sp) - lw x9, 9 *4(sp) - lw x10, 10*4(sp) - lw x11, 11*4(sp) - lw x12, 12*4(sp) - lw x13, 13*4(sp) - lw x14, 14*4(sp) - lw x15, 15*4(sp) - lw x16, 16*4(sp) - lw x17, 17*4(sp) - lw x18, 18*4(sp) - lw x19, 19*4(sp) - lw x20, 20*4(sp) - lw x21, 21*4(sp) - lw x22, 22*4(sp) - lw x23, 23*4(sp) - lw x24, 24*4(sp) - lw x25, 25*4(sp) - lw x26, 26*4(sp) - lw x27, 27*4(sp) - lw x28, 28*4(sp) - lw x29, 29*4(sp) - lw x30, 30*4(sp) - lw x31, 31*4(sp) - - addi sp, sp, 136 - mret \ No newline at end of file