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启用中断，开始调中断软件

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RuigeLee
2024-10-28 18:01:25 +08:00
parent ce18e90304
commit 7bcd0aaca0
6 changed files with 52 additions and 304 deletions
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9
Makefile
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@@ -88,10 +88,15 @@ sw:
riscv64-unknown-elf-objcopy -O binary ./tb/sw/build/test.elf ./tb/sw/build/test.bin
riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata ./tb/sw/build/test.elf > ./tb/sw/build/test.dump
# riscv64-unknown-elf-objdump -h ./tb/sw/build/test.elf > ./tb/sw/build/test.dump
riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/test.elf > ./tb/sw/build/test.dump
riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/test.elf ./tb/sw/build/test.verilog
# riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf
riscv64-unknown-elf-readelf -a ./tb/sw/build/test.elf
riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf
riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/test.elf ./tb/sw/build/test.verilog
sed -i 's/@800/@000/g' ./tb/sw/build/test.verilog
fst: