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处理完IO亚稳态问题，测试完成

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RuigeLee
2024-04-14 20:33:10 +08:00
parent 93bbeabd20
commit 7bc3136790
1 changed files with 14 additions and 14 deletions
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28
src/main/scala/backBoard/LocalRegisters.scala
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@@ -126,19 +126,17 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
def gp: Int def gp: Int
val flitNum = 32
require(flitNum <= 128)
val in = IO(Input(UInt((8*gp).W))) val in = IO(Input(UInt((8*gp).W)))
val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U((log2Ceil(256/flitNum)).W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) )) val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U((log2Ceil(256/32)).W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) ))
val flitTrigger = Wire(Vec(9, Bool())) val flitTrigger = Wire(Vec(9, Bool()))
flitTrigger(0) := ~RegNext(flitTrigger(0)) flitTrigger(0) := ~RegNext(flitTrigger(0))
// flitTrigger(1) := usTrigger // flitTrigger(1) := usTrigger
flitTrigger(1) := flitCnt(1) >= (256/flitNum-1).U flitTrigger(1) := flitCnt(1) >= (256/32-1).U
when( ~RegNext(usTrigger) & usTrigger ){ when( ~RegNext(usTrigger) & usTrigger ){
when( flitTrigger(1) ){ when( flitTrigger(1) ){
flitCnt(1) := 0.U flitCnt(1) := 0.U
@@ -197,33 +195,35 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
for( i <- 0 until 8 ) { for( i <- 0 until 8 ) {
val flitter = RegInit(VecInit( Seq.fill(flitNum){false.B})) val flitter = RegInit(VecInit( Seq.fill(32){false.B}))
val flitHi = RegInit(0.U((log2Ceil(flitNum+1)).W)) val flitHi = RegInit(0.U((log2Ceil(32)).W))
( 0 until 9 ).map{ k => ( 0 until 9 ).map{ k =>
when( digitalFilter === k.U ){ when( digitalFilter === k.U ){
when( (if( k == 0 ){ true.B } else {~RegNext(flitTrigger(k)) & flitTrigger(k)}) ){ when( (if( k == 0 ){ true.B } else {~RegNext(flitTrigger(k)) & flitTrigger(k)}) ){
flitter(0) := in(i+8*j) flitter(0) := in(i+8*j)
(1 until flitNum).map{ k => (1 until 32).map{ k =>
flitter(k) := flitter(k-1) flitter(k) := flitter(k-1)
} }
when( (~flitter(flitNum-1) & ~in(i+8*j)) | (flitter(flitNum-1) & in(i+8*j)) ){ when( (~flitter(31) & ~flitter(0)) | (flitter(31) & flitter(0)) ){
flitHi := flitHi flitHi := flitHi
} .elsewhen( ~flitter(flitNum-1) & in(i+8*j) ){ } .elsewhen( ~flitter(31) & flitter(0) ){
flitHi := flitHi + 1.U flitHi := flitHi + 1.U
} .elsewhen( flitter(flitNum-1) & ~in(i+8*j) ){ } .elsewhen( flitter(31) & ~flitter(0) ){
flitHi := flitHi - 1.U flitHi := flitHi - 1.U
} }
when( flitHi >= (flitNum*4/5).U ){ when( flitHi >= 26.U ){
digitalIn(i) := true.B digitalIn(i) := true.B
} .elsewhen( flitHi <= (flitNum/5).U ){ } .elsewhen( flitHi <= 6.U ){
digitalIn(i) := false.B digitalIn(i) := false.B
} }
assert( flitHi <= flitNum.U ) val fliterCnt = WireDefault( VecInit( (1 until 32).map{ k => flitter(k) }) )
assert( flitter.count( (k:Bool) => k === true.B ) === flitHi )
assert( flitHi <= 31.U )
assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi )
} }
} }