现场基本恢复

src/main/scala/backBoard/shin/ShinTop.scala

@@ -31,16 +31,7 @@ class ShinTopIO extends Bundle{
   val sram_w = Vec( 4, new SRAM2kWRIO) //QSPI
   val sram_r = Vec( 4, new SRAM2kRDIO) //QSPI
 
-  val sram = MixedVec(
-     Flipped(Vec(4, new SRAM2kIO)),
-     Flipped(Vec(4, new SRAM2kIO)),
-     Flipped(Vec(4, new SRAM2kIO)),
-     Flipped(Vec(4, new SRAM2kIO)),
-     Flipped(Vec(2, new SRAM2kIO)),
-     Flipped(Vec(2, new SRAM2kIO)),
-     Flipped(Vec(2, new SRAM2kIO)),
-     Flipped(Vec(2, new SRAM2kIO)),
-  )
+
 }
 
 
@@ -66,6 +57,17 @@ class ShinTop extends Module{
     Module( new SMUnit(depth = 2) ),
   )
 
+  val sram = Seq(
+    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
+    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
+    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
+    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
+    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
+    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
+    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
+    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
+  )
+
 
   smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
   smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
@@ -109,14 +111,39 @@ class ShinTop extends Module{
   smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
   smUnit(7).io.deq := slaveParser.io.uSMdeq(3)
 
-  smUnit(0).io.sram <> io.sram(0)
-  smUnit(1).io.sram <> io.sram(1)
-  smUnit(2).io.sram <> io.sram(2)
-  smUnit(3).io.sram <> io.sram(3)
-  smUnit(4).io.sram <> io.sram(4)
-  smUnit(5).io.sram <> io.sram(5)
-  smUnit(6).io.sram <> io.sram(6)
-  smUnit(7).io.sram <> io.sram(7)
+
+
+
+
+  for( i <- 0 until 4 ){
+    for( j <- 0 until 4 ){
+      sram(i)(j).io.clockr := clock.asBool
+      sram(i)(j).io.clockw := clock.asBool
+
+      smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
+      sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
+      sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
+      sram(i)(j).io.enw   := smUnit(i).io.sram(j).wr.enw
+      sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
+      sram(i)(j).io.enr   := smUnit(i).io.sram(j).rd.enr
+    }
+  }
+
+  for( i <- 4 until 8 ){
+    for( j <- 0 until 2 ){
+      sram(i)(j).io.clockr := clock.asBool
+      sram(i)(j).io.clockw := clock.asBool
+
+      smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
+      sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
+      sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
+      sram(i)(j).io.enw   := smUnit(i).io.sram(j).wr.enw
+      sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
+      sram(i)(j).io.enr   := smUnit(i).io.sram(j).rd.enr
+    }    
+  }
+
+
 
 
   slaveParser.io.downIn  <> io.downIn
@@ -127,14 +154,14 @@ class ShinTop extends Module{
   slaveParser.io.timeStamp := io.timeStamp
 
 
-  slaveParser.io.trigAddr(0) := "hffff".U
-  slaveParser.io.trigAddr(1) := "hffff".U
-  slaveParser.io.trigAddr(2) := "hffff".U
-  slaveParser.io.trigAddr(3) := "hffff".U
-  slaveParser.io.trigAddr(4) := "hffff".U
-  slaveParser.io.trigAddr(5) := "hffff".U
-  slaveParser.io.trigAddr(6) := "hffff".U
-  slaveParser.io.trigAddr(7) := "hffff".U
+  slaveParser.io.trigAddr(0) := "hff".U
+  slaveParser.io.trigAddr(1) := "hff".U
+  slaveParser.io.trigAddr(2) := "hff".U
+  slaveParser.io.trigAddr(3) := "hff".U
+  slaveParser.io.trigAddr(4) := "hff".U
+  slaveParser.io.trigAddr(5) := "hff".U
+  slaveParser.io.trigAddr(6) := "hff".U
+  slaveParser.io.trigAddr(7) := "hff".U