现场基本恢复

src/main/scala/backBoard/shin/ShareSRAM.scala

@@ -83,4 +83,69 @@ class ShareSRAMDP extends BlackBox with HasBlackBoxInline {
       |
       |endmodule
     """.stripMargin)
+}
+
+
+
+
+class ShareSRAM2k extends BlackBox with HasBlackBoxInline {
+
+  class ShareSRAM2kIO extends Bundle{
+    val dataw = Input( UInt(8.W) )
+    val addrw = Input(UInt(15.W))
+    val enw   = Input(Bool())
+
+    val datar = Output( UInt(8.W) )
+    val addrr = Input(UInt(15.W))
+    val enr   = Input(Bool())
+
+    val clockr = Input(Bool())
+    val clockw = Input(Bool())
+
+  }
+  val io: ShareSRAM2kIO = IO(new ShareSRAM2kIO)
+
+ setInline("ShareSRAM2k.v",
+              """
+
+  | module ShareSRAM2k(
+  |   	input [7:0] dataw,
+  |   	input [10:0] addrw,
+  |   	input enw,
+  |   
+  |   	output [7:0] datar,
+  |   	input [10:0] addrr,
+  |   	input enr,
+  |   
+  |   	input clockr,
+  |     input clockw
+  |   );
+  |   
+  |   	reg [7:0] ram[0:2047];
+  |   	reg [7:0] data_r_reg;
+  |   
+  |   	always @(posedge clockw) begin
+  |   		if(enw) begin
+  |   			ram[addrw] <= #1 dataw;
+  |   			end
+  |     end
+  |   
+  |     always @(posedge clockr) begin
+  |         if(enr) begin
+  |              data_r_reg <= #1 ram[addrr];
+  |         end
+  |     end
+  |   
+  |   	assign datar = data_r_reg;
+  |   
+  |   initial begin
+  |   	for ( integer i = 0; i < 2048; i = i + 1 ) begin
+  |   		ram[i] = $random;
+  |   	end
+  |   
+  |   	data_r_reg = $random;
+  |   end
+  |    
+  | endmodule
+    """.stripMargin)
 }