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现场基本恢复

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This commit is contained in:
Ruige Lee
2025-04-25 17:00:51 +08:00
parent dc67286e23
commit 7b63b07408
5 changed files with 592 additions and 35 deletions
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65
src/main/scala/backBoard/shin/ShareSRAM.scala
View File

@@ -83,4 +83,69 @@ class ShareSRAMDP extends BlackBox with HasBlackBoxInline {
|
|endmodule
""".stripMargin)
}
class ShareSRAM2k extends BlackBox with HasBlackBoxInline {
class ShareSRAM2kIO extends Bundle{
val dataw = Input( UInt(8.W) )
val addrw = Input(UInt(15.W))
val enw = Input(Bool())
val datar = Output( UInt(8.W) )
val addrr = Input(UInt(15.W))
val enr = Input(Bool())
val clockr = Input(Bool())
val clockw = Input(Bool())
}
val io: ShareSRAM2kIO = IO(new ShareSRAM2kIO)
setInline("ShareSRAM2k.v",
"""
| module ShareSRAM2k(
| input [7:0] dataw,
| input [10:0] addrw,
| input enw,
|
| output [7:0] datar,
| input [10:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [7:0] ram[0:2047];
| reg [7:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| ram[addrw] <= #1 dataw;
| end
| end
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 ram[addrr];
| end
| end
|
| assign datar = data_r_reg;
|
| initial begin
| for ( integer i = 0; i < 2048; i = i + 1 ) begin
| ram[i] = $random;
| end
|
| data_r_reg = $random;
| end
|
| endmodule
""".stripMargin)
}

79
src/main/scala/backBoard/shin/ShinTop.scala
View File

@@ -31,16 +31,7 @@ class ShinTopIO extends Bundle{
val sram_w = Vec( 4, new SRAM2kWRIO) //QSPI
val sram_r = Vec( 4, new SRAM2kRDIO) //QSPI
val sram = MixedVec(
Flipped(Vec(4, new SRAM2kIO)),
Flipped(Vec(4, new SRAM2kIO)),
Flipped(Vec(4, new SRAM2kIO)),
Flipped(Vec(4, new SRAM2kIO)),
Flipped(Vec(2, new SRAM2kIO)),
Flipped(Vec(2, new SRAM2kIO)),
Flipped(Vec(2, new SRAM2kIO)),
Flipped(Vec(2, new SRAM2kIO)),
)
}
@@ -66,6 +57,17 @@ class ShinTop extends Module{
Module( new SMUnit(depth = 2) ),
)
val sram = Seq(
for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
)
smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
@@ -109,14 +111,39 @@ class ShinTop extends Module{
smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
smUnit(7).io.deq := slaveParser.io.uSMdeq(3)
smUnit(0).io.sram <> io.sram(0)
smUnit(1).io.sram <> io.sram(1)
smUnit(2).io.sram <> io.sram(2)
smUnit(3).io.sram <> io.sram(3)
smUnit(4).io.sram <> io.sram(4)
smUnit(5).io.sram <> io.sram(5)
smUnit(6).io.sram <> io.sram(6)
smUnit(7).io.sram <> io.sram(7)
for( i <- 0 until 4 ){
for( j <- 0 until 4 ){
sram(i)(j).io.clockr := clock.asBool
sram(i)(j).io.clockw := clock.asBool
smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
sram(i)(j).io.enw := smUnit(i).io.sram(j).wr.enw
sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
sram(i)(j).io.enr := smUnit(i).io.sram(j).rd.enr
}
}
for( i <- 4 until 8 ){
for( j <- 0 until 2 ){
sram(i)(j).io.clockr := clock.asBool
sram(i)(j).io.clockw := clock.asBool
smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
sram(i)(j).io.enw := smUnit(i).io.sram(j).wr.enw
sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
sram(i)(j).io.enr := smUnit(i).io.sram(j).rd.enr
}
}
slaveParser.io.downIn <> io.downIn
@@ -127,14 +154,14 @@ class ShinTop extends Module{
slaveParser.io.timeStamp := io.timeStamp
slaveParser.io.trigAddr(0) := "hffff".U
slaveParser.io.trigAddr(1) := "hffff".U
slaveParser.io.trigAddr(2) := "hffff".U
slaveParser.io.trigAddr(3) := "hffff".U
slaveParser.io.trigAddr(4) := "hffff".U
slaveParser.io.trigAddr(5) := "hffff".U
slaveParser.io.trigAddr(6) := "hffff".U
slaveParser.io.trigAddr(7) := "hffff".U
slaveParser.io.trigAddr(0) := "hff".U
slaveParser.io.trigAddr(1) := "hff".U
slaveParser.io.trigAddr(2) := "hff".U
slaveParser.io.trigAddr(3) := "hff".U
slaveParser.io.trigAddr(4) := "hff".U
slaveParser.io.trigAddr(5) := "hff".U
slaveParser.io.trigAddr(6) := "hff".U
slaveParser.io.trigAddr(7) := "hff".U

23
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -399,18 +399,19 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val isWRSM6 = (addrw(14,11) === "b0111".U)
when( downRecParser.io.subMsgReq.fire ){
when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
addrw := downRecParser.io.subMsgReq.bits.address
}
}
val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
( ~isDownRecPing & (downSubMsgInfo(0).devIndex === localDevIndex) & ( (downSubMsgInfo(0).operator === 1.U) | (downSubMsgInfo(0).operator === 3.U) )) |
( isDownRecPing & (downSubMsgInfo(1).devIndex === localDevIndex) & ( (downSubMsgInfo(1).operator === 1.U) | (downSubMsgInfo(1).operator === 3.U) ))
)
when( downRecParser.io.subMsgReq.fire & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
addrw := downRecParser.io.subMsgReq.bits.address
} .elsewhen( isWrite ){
addrw := addrw + 1.U
}
io.sram_w(0).enw := isWrite & isWRSM0
@@ -458,8 +459,12 @@ trait SlaveParserRW{ this: SlaveParserBase =>
//读出uSM
val isRead =
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (upSubMsgInfo(0).devIndex === localDevIndex) & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U)) |
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
(~isUpRecPing & upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U)) |
( isUpRecPing & upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 2.U | upSubMsgInfo(1).operator === 3.U))
) |
((upRecParser.io.stateNext === STATE_PAYLOAD_DATA) & (upRecParser.io.subMsgReq.bits.devIndex === localDevIndex) & (upRecParser.io.subMsgReq.bits.operator === 2.U | upRecParser.io.subMsgReq.bits.operator === 3.U))
)
val addrr = Reg(UInt(15.W))
val readSMAddr = Mux1H(Seq(
@@ -475,6 +480,8 @@ trait SlaveParserRW{ this: SlaveParserBase =>
when( upRecParser.io.subMsgReq.fire & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
addrr := upRecParser.io.subMsgReq.bits.address
} .elsewhen( isRead ){
addrr := addrr + 1.U
}
val upStreamData = Mux1H(Seq(