dout增加公共端IO

2024-06-14 19:00:41 +08:00
parent 715a1e6c08
commit 7aa7ea7ec6
10 changed files with 5 additions and 1 deletions
--- a/src/main/verilog/do16_top.v
+++ b/src/main/verilog/do16_top.v
@@ -22,7 +22,8 @@ module do16_top(
  output        LED_PR,
  output [15:0] out,
  input         flt_0,
-  input         flt_1
+  input         flt_1,
+  input         v24Det

 );

@@ -297,6 +298,7 @@ DOut16 i_dout16(
  .out(out),
  .flt_0(flt_0),
  .flt_1(flt_1),
+  .v24Det(v24Det),

  .io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out),
  .io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid),